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AD6676EBZ 数据表(PDF) 32 Page - Analog Devices |
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AD6676EBZ 数据表(HTML) 32 Page - Analog Devices |
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32 / 90 page  AD6676 Data Sheet Rev. D | Page 32 of 90 –140 –142 –144 –146 –148 –150 –152 –154 –156 –158 –160 140 150 160 170 180 190 200 210 220 INPUT FREQUENCY (MHz) SHUFFLE EVERY 1 ADC CYCLE IBN = –75.5dBFS SHUFFLE EVERY 4 ADC CYCLES IBN = –76.3dBFS SHUFFLE DISABLED IBN = –77.4dBFS Figure 87. NSD Performance of the Various Shuffling Settings with No Signal; Threshold Set to 0 (Shuffler Is Always Enabled); FIF = 180 MHz, BW = 80 MHz, FADC = 3.2 GHz, LEXT = 43 nH –140 –142 –144 –146 –148 –150 –152 –154 –156 –158 –160 140 150 160 170 180 190 200 210 220 INPUT FREQUENCY (MHz) SHUFFLE EVERY 1 ADC CYCLE IBN = –73.6dBFS SHUFFLE EVERY 4 ADC CYCLES IBN = –74.0dBFS SHUFFLE DISABLED IBN = –74.6dBFS Figure 88. NSD Performance of the Various Shuffling Settings with a −1 dBFS Signal; Threshold Set to 0 (Shuffler Is Always Enabled); FIF = 180 MHz, BW = 80 MHz, FADC = 3.2 GHz, LEXT = 43 nH The degradation in NSD performance is also dependent on the input signals amplitude; thus, it is important to select a shuffling rate and threshold setting that result in an optimum trade-off between large signal linearity performance and low signal level in-band noise performance. Figure 89 shows how the in-band noise (dBFS) degrades at increasing signal levels for the same settings used in Figure 87. In this example, a continuous wave tone is placed just above the pass band with its power swept from −40 dBFS to −1 dBFS. At low signal levels (less than −20 dBFS), the degradation in in-band noise performance is dependent on the shuffling rate. At higher signal levels (greater than−20 dBFS), the degradation is a result of increased colored noise falling in the pass band. Selecting a shuffle rate of every two ADC cycles with a threshold in the range of 4 or 5 is a good compromise, as shown in Figure 90. –74 –75 –76 –77 –78 –79 –800 –40 –35 –30 –25 –20 –15 –10 –5 0 INPUT POWER (dBFS) SHUFFLING EVERY 1 ADC CYCLE SHUFFLING EVERY 2 ADC CYCLES SHUFFLING EVERY 4 ADC CYCLES SHUFFLING EVERY 3 ADC CYCLES SHUFFLING DISABLED Figure 89. Pass Band Degradation in IBN (dBFS) as a Continuous Wave Tone at 225 MHz, Swept from −40 dBFS to −1 dBFS with Different Shuffling Rate Settings, Threshold Set to 0, FIF = 180 MHz, BW = 80 MHz, FADC = 3.2 GHz, LEXT = 43 nH –74 –75 –76 –77 –78 –79 –80 –40 –35 –30 –25 –20 –15 –10 –5 0 INPUT POWER (dBFS) SHUFFLING DISABLED SHUFFLING EVERY 2 ADC CYCLES THRESHOLD = 4 SHUFFLING EVERY 2 ADC CYCLES THRESHOLD = 5 Figure 90. IBN vs. Input Power Performance for Threshold Settings of 4 and 5 When Configured for Shuffle Every Two ADC Cycles After a particular shuffling configuration is selected, the effects on the Σ-Δ ADC performance remain repeatable over time and among different devices Σ-Δ ADC Profile Feature The AD6676 includes a feature that allows the Σ-Δ ADC to store up to four different profile settings that can be recalled quickly via Register 0x118 without recalibrating the Σ-Δ ADC. Calibration of each of the different profiles specified in Register 0x115 occurs during the device initialization phase with each profile consisting of the following various application parameters: BW, FIF, IDAC1FS, and MRGN. FADC, along with the decimation filter and JESD204B settings, remains common to ensure that the JESD204B link is maintained when switching between profile settings. Note that the Σ-Δ ADC is operational with the updated profile settings within 1 μs upon receipt of the SPI command. |
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