AD6676EBZ datasheet(62/90 Pages) AD

62 / 90 page

AD6676

Data Sheet

Rev. D | Page 62 of 90

Table 26. SPI Initialization Example, fCLK = 3.2 GHz, FIF = 250 MHz, BW = 100 MHz, IDAC1FS = 2 mA, MRGN_L = MRGN_U = 10 MHz,

MRGN_IF = 1 MHz, fDATA_IQ = 200 MSPS with Decimate by 16

Step

Address (Hex)1

Write Value1

Comments

0x000

0x99

Software reset, 4-wire SPI.

Wait 2 ms for SPI initialization after reset.

CLK path or CLK SYN initialization (see Table 28 for using external RF clock; refer to Table 27 for

using internal CLK SYN.)

0x1E7

0x04

Select LVDS input for SYNCINB receiver.

0x1C0

0x01

JESD204 (DID = 1, optional).

0x1C1

0x05

JESD204 (BID = 5, optional).

0x1C3

0x01

JESD204B (SCR = 0, L = 2).

0x1C4

0x01

JESD204B (F = 2).

0x1C5

0x0F

JESD204B (K = 16).

0x1EC

0xBD

Configure PHY output driver.

0x100

0x80

Set FADC to 3200 MHz.

0x101

0x0C

Set FADC to 3200 MHz.

0x102

0xFA

Set the IF to 250 MHz.

0x103

0x00

Set the IF to 250 MHz.

0x104

0x64

Set the BW_0 to 100 MHz.

0x105

0x00

Set the BW_1 to 0 MHz.

0x106

0x13

Set LEXT to 19 nH.

0x107

0x0a

Set MRGN_L to 10 MHz.

0x108

0x0a

Set MRGN_U to 10 MHz.

0x109

0x01

Set MRGN_IF to 1 MHz.

0x10A

0x20

Set IDAC1FS to 2 mA, resulting in PIN_0dBFS = −8 dBm.

0x116

0x0A

Initiate RESON1 calibration.

Wait 250 ms for fCLK = 3.2 GHz. Note that the wait time scales with fCLK proportionally such that

the wait = 400 ms for fCLK = 2 GHz.

Read back Register 0x117 to see if Bit 0 has been set to 1 indicating ADC calibration is complete. If

not, proceed to Step 25.

0x11A

0x01

Force end of calibration (toggle Bit 0).

0x11A

0x00

Force end of calibration (toggle Bit 0).

Return to Step 22 and attempt again. Make two attempts before breaking out of loop if the

calibration problem persists.

0x140

0x03

Set DEC_MODE to user defined setting of decimate by 16. Note that coarse and fine NCO

settings (SPI Register 0x141 and SPI Register 0x142) are automatically set based on FADC and IF

settings (Register 0x100 to Register 0x103).

0x116

0x17

Calibrate and initiate ADC; set-up and initiate JESD204B.

Wait 250 ms for fCLK = 3.2 GHz. Note that wait time scales with fCLK proportionally such that the

wait = 400 ms for fCLK = 2 GHz.

Read back Register 0x117 to see if Bit 0 has been set to 1 indicating ADC calibration is complete. If

not, proceed to Step 31.

0x11A

0x01

Force end of calibration (toggle Bit 0).

0x11A

0x00

Force end of calibration (toggle Bit 0).

Return to Step 28 and attempt again. Make two attempts before breaking out of loop if the

calibration problem persists.

Insert the optional AGC and nondefault shuffler settings (see Table 29 and Table 30 for an example).

1 Cells in the Address (Hex) column and Write Value column were left intentionally blank.

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