AD6676EBZ datasheet(31/90 Pages) AD

31 / 90 page

Data Sheet

AD6676

Rev. D | Page 31 of 90

Σ-Δ ADC Adaptive Shuffler

The AD6676 includes a programmable adaptive shuffler that

improves the SFDR and IMD performance of the Σ-Δ ADC

under large signal conditions. As shown in Figure 68, the adaptive

shuffler randomizes the selection of the unit elements used by

the feedback DACs to reconstruct the output signal of the

quantizer. Both static and dynamic mismatch errors associated

with the quantizer and feedback DACs are dithered such that

the spurious contribution is spread across a wider frequency

span. Figure 86 compares the improved IMD performance for a

two tone excitation when the shuffler is enabled and disabled.

–120

–100

–80

–60

–40

–20

–120

–100

–80

–60

–40

–20

140

150

160

170

180

190

200

210

220

FREQUENCY (MHz)

ADAPTIVE SHUFFLING

DISABLED

ADAPTIVE SHUFFLING ENABLED

SHUFFLE EVERY

ONE ADC CLOCK CYCLE

(0x342 = 0xF5, 0x343 = 0xFF)

Figure 86. IMD Performance when Shuffler Is Disabled vs. Enabled for Two

CW Tones at −8 dBFS, (FIF = 180 MHz, BW = 80 MHz, FADC = 3.2 GHz, LEXT = 43 nH)

Although the shuffler improves the SFDR and IMD performance,

it does so at the expense of the in-band NSD performance. For

this reason, both the degree of shuffling as well as the enabling

threshold relative to the quantizer output code is user programmable,

allowing optimization for a target application. The shuffling rate

is variable from 1 to 4 ADC clock cycles (1/FADC). The shuffler

remains enabled for a fixed amount of clock cycles from the

instant that the input signal falls below this threshold and

remains below it.

The enabling threshold is relative to the quantizer code and

represents the peak absolute value that triggers the shuffler. The

quantizer can produce an output code ranging from −8 to +8,

therefore the threshold can assume a value between 0 to 8. The

4-bit value is set via Register 0x342 or Register 0x343. A

hexadecimal value of 0x0 sets the shuffler to always enabled

whereas a value of 0xF effectively disables the shuffler.

The 4-bit fields in Register 0x342 and Register 0x343 set the

threshold value based on the shuffling rate selected. Set only the

4-bit field pertaining to the selected shuffling rate while the

remaining nonapplicable 4-bit fields set to 0xF. Disable the shuffler

by setting all the 4-bit fields to 0xF, the highest threshold setting.

Table 9 shows the SPI register settings for the various shuffling

modes when the threshold is set to its default setting of 5. Other

threshold values ranging from 3 to 8 are also possible. Table 10

shows the input power level that triggers the shuffler for different

threshold value settings when driven by a continuous wave tone.

Table 9. Default SPI Register Settings for Adaptive Shuffling

Shuffling Rate

FADC

0xF5

0xFF

FADC/2

0x5F

0xFF

FADC/3

0xFF

0xF5

FADC/4

0xFF

0x5F

Disable shuffler

0xFF

Table 10. Threshold Setting Values that Trigger the Shuffler

for a Continuous Wave Tone

PIN (dBFS)

Threshold Setting

−3

−5

−7

−10

−14

−20

When enabled, the shuffler can introduce colored noise into the

pass band spectrum. This additional noise is a result of the

increased switching activity within the Σ-Δ ADC core along

with the pseudorandom element selection process, thus resulting

in signal level dependent colored noise at frequency offsets related

to the shuffling rate. Figure 87 highlights the effect of the colored

noise between shuffle every four clock cycles vs. one cycle with

and without a large signal continuous wave tone present and the

shuffling threshold set to 0.

Typically, the shuffling threshold is set in the range of 4 to 6. This

example serves to highlight the colored noise effects of shuffling.

Selecting a higher threshold setting is preferable when trying to

preserve the NSD performance. For this reason, the AD6676

default threshold setting is 5 with the shuffle every clock cycle

option.

The four-cycle option introduces visible noise humps with a

−1 dBFS signal level. This colored noise is at an offset of

fCLK/128, resulting from the pseudorandom element selection

process. Other shuffling options also introduce colored noise

but at a greater frequency offset that are related to the shuffling

rate factor (SRF) as described by the following equation:

Frequency Offset = fCLK/(32 × SRF)

(5)

The effect of this colored noise is worthy of consideration when

selecting the shuffling rate and threshold. For example, sweeping

a −1 dBFS continuous wave tone across the usable IF pass band

region while monitoring the NSD characteristics is helpful to

identify what shuffling rate may have the least impact on the

NSD performance.

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