AD6676EBZ datasheet(4/90 Pages) AD

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AD6676

Data Sheet

Rev. D | Page 4 of 90

The band-pass Σ-Δ ADC of the AD6676, which operates

between 2.0 GHz to 3.2 GHz, provides exceptional instantaneous

dynamic range and inherent antialiasing capability. Its in-band

frequency response typically maintains better than 1 dB pass

band flatness with out-of-band peaking better than 0.5 dB. An

integrated digital peak detector enables the instantaneous signal

power to be monitored over a wide band (shortly after digitization),

thus providing AGC capability to cope quickly with large in-band

or out-of-band blockers.

The AD6676 includes various AGC monitoring and control

features along with an internal 27 dB step attenuator in 1 dB

steps. A flexible AGC port with digital input/output pins allows

fast control of the AD6676 on-chip step attenuator and/or

updates on the input signal via status flags. These features,

along with the high instantaneous dynamic range, can

significantly simplify AGC implementation compared to

traditional narrow-band IF approaches that often require

separate AGC capability for RF and IF protection.

In addition to reducing system complexity, the AD6676 enables

significant space and power consumption savings for next

generation multiple input/multiple output (MIMO) receiver

architectures. The AD6676 is available in an 8 × 10 ball array

WLCSP package that is approximately 4.3 mm × 5.0 mm, with

a JESD204B serial interface that allows simple interfacing to the

host processor.

Its low power consumption of 1.2 W compares favorably to IF

sampling ADCs with similar bandwidth (BW) and dynamic

range capabilities even without considering the added power

savings from the elimination of an entire IF strip. The AD6676

features multichip synchronization that allows synchronization

to within a fraction of an output data sample. For time-domain

duplex (TDD) applications, the AD6676 features a fast power-

up/power-down mode that further reduces power consumption

while still maintaining multichip synchronization. Power

savings of up to 60% or 42% is achievable with recovery times of

11.5 μs or 2.5 μs, depending on the device configuration.

Auxiliary blocks include an on-chip PLL clock multiplier to

generate the Σ-Δ ADC clock. For applications that require

better phase noise performance, an external differential RF

clock source may also be used. The SPI port programs numerous

parameters of the AD6676, allowing the device to be optimized

for a variety of applications.

The AD6676 is available in an 80-ball WLCSP package with an

optimized pinout that enables low cost printed circuit board

(PCB) manufacturing. The device operates from a 1.1 V and

2.5 V supply with a total typical power consumption of 1.2 W at

3.2 GSPS operation. This product is protected by several United

States patents. Contact Analog Devices, Inc., for further

information.

PRODUCT HIGHLIGHTS

Industry leading dynamic range enables high performance,

reconfigurable heterodyne (or direct sampling VHF)

software defined radios with high AGC-free range.

Continuous time, band-pass Σ-Δ ADC supports IFs from

70 MHz to 450 MHz with IF signal bandwidths of up to

160 MHz and reduces IF filtering requirements.

The high instantaneous dynamic range and oversampling

nature of the Σ-Δ ADC significantly reduces the IF filter

complexity.

On-chip 27 dB digital attenuator with easy to drive resistive

input simplifies interface to RF/IF components.

Small 4.3 mm × 5.0 mm package, simple interface, and

integrated digital attenuator and clock synthesizer save

PCB space.

Low input full-scale level of −2 dBm (or less) enables 3.3 V

RF/IF component lineups at reduced P1dB and power.

Fast power saving mode supports TDD protocols.

Unique profile mode allows the AD6676 to switch between

up to four different ADC IF/BW configurations in 1 μs.

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