AD6676EBZ datasheet(44/90 Pages) AD

44 / 90 page

AD6676

Data Sheet

Rev. D | Page 44 of 90

UPPER THRESHOLD (PKTTHR1)

LOWER THRESHOLD (LOWTHRH)

FLAG1

FLAG0

DWELL TIME

TIMER RESET BY

RISE ABOVE

LOWER

THRESHOLD

TIMER COMPLETES BEFORE

SIGNAL RISES ABOVE

LOWER THRESHOLD

DWELL TIME

Figure 114. Example of Flag Behavior as Signal Envelope Crosses Upper and Lower Threshold Settings

Table 17. Power Saving for 3.0 GSPS Operation with CLKSYN Enabled and 125 MSPS IQ Rate (Single JESD204B Lane)

Power State at 3 GSPS

IVDD2 (mA)

IVDD1+, IVDDC+ IVDDL (mA)

IVDDD (mA)

PTOTAL (mW)

Percent (%) Power Savings

STDBY_SLOW

162

216

461

STDBY_FAST

175

221

673

Power Down

2.6

Not applicable

Power Up

146

433

310

1182

Not applicable

GPIO FUNCTIONALITY

The AGCx pins can also be configured for basic GPIO

functionality via Register 0x1B0 to Register 0x1B4. Register 0x1B0

determines which pins are used for GPIO functionality, whereas

output. If the pin serves as an output, Register 0x1B2 determines

the high or low state, and Register 0x1B3 reads back the state of

these designated output pins. Lastly, if an AGCx pin serves as an

input, Register 0x1B4 reads back the state of this pin.

POWER SAVING MODES

The AD6676 features two SPI configurable and selectable power

savings modes. The first mode is a sleep mode where the AD6676

is placed in a low power state for extended periods, and the

second mode is a standby mode where the AD6676 enters a

reduced power state but still keeps the JESD204B link and digital

clocks active to ensure multichip synchronization (or fixed

latency) during fast power cycling. Both sleep mode and standby

mode can be entered via a SPI write operation to the PD_MODE

bits in the DEVICE_CONFIG register (Register 0x002; Bits[1:0]).

Note that, depending on whether sleep or standby mode is

selected, various functional blocks within the Σ-Δ ADC itself

are either powered down, placed in a low bias state, or remain

powered.

The standby mode is also controllable via a user designated

AGCx pin for faster and more precise power cycling. This

feature is particularly useful for TDD-based communication

protocols, allowing the host processor to quickly power cycle

the AD6676 during transmit bursts. The PD_PIN_CTRL

designates the AGC pin.

The standby register (Register 0x150) powers down different

functional blocks during standby mode. However, all functional

blocks that affect the clock generation, distribution and the

JESD204B link remain enabled to maintain constant latency

while in standby. The only exception is STBY_VSS2GEN

(Register 0x150, Bit 6) where a trade-off exists in power savings

vs. wake-up time, depending on whether the negative voltage

generator is placed in standby.

Table 17 shows the realized power savings for the different

power savings modes at 3.0 GSPS operation with the AD6676

configured for 125 MSPS IQ output and the internal clock

synthesizer enabled. Note that STDBY_FAST and STDBY_SLOW

correspond to whether the STBY_VSS2GEN bit is enabled or

disabled during standby. Note that an additional 18% power

savings can be achieved when powering down the

STBY_VSS2GEN bit.

Although the AD6676 can enter into standby quickly, it does

require a few microseconds to exit standby. Figure 115 shows

that the AD6676 can achieve a low power state within 100 ns.

Figure 116 and Figure 117 show the wake-up time between the

STDBY_FAST and STDBY_SLOW cases to achieve 1% envelope

settling accuracy being around 2.5 μs and 11.5 μs, respectively.

The phase response is not shown because it settles faster than

the envelope response. Note that the digital data path is enabled

for these time domain figures such that the setting time

responses can be observed.

AD6676EBZ 数据表(PDF) 44 Page - Analog Devices

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