AD6676EBZ datasheet(35/90 Pages) AD

35 / 90 page

Data Sheet

AD6676

Rev. D | Page 35 of 90

1.00

0.25

0.50

0.75

160

140

120

100

SAMPLE

Figure 97. Wide Envelope Response for 6 dB Attenuator Step Change with

fDATA_IQ = 250 MSPS, Resulting Sample Period of 4 ns

1.00

0.25

0.50

0.75

SAMPLE

Figure 98. Zoom In Envelope Response for 6 dB Attenuator Step Change with

fDATA_IQ = 250 MSPS, Resulting Sample Period of 4 ns

CLOCK SYNTHESIZER

The AD6676 includes an on-chip clock synthesizer capable of

generating the clock for the Σ-Δ ADC and digital circuitry. The

entire synthesizer is integrated on-chip, including the loop filter

and VCO. Figure 99 shows a functional block diagram of the

various synthesizer subblocks along with the relevant SPI registers.

The clock synthesizer uses a standard integer-N architecture to

generate a 2.94 GHz to 3.2 GHz ADC clock from a 10 MHz to

320 MHz reference input.

Configuring the clock synthesizer requires numerous SPI

commands to program settings and to initiate calibrations. The

SPI sequence to configure the AD6676 for a particular operating

mode, including the SPI operations associated with the clock

synthesizer, is most easily obtained from the software tool that

comes with the AD6676EBZ development platform. This tool

allows the SPI sequence used to configure the AD6676 to be

saved to a file for later use.

Note that if the clock synthesizer is used to supply the ADC clock,

the clock synthesizer must be configured first, before any other

blocks are enabled. Also note that because the clock synthesizer

sequence involves calibrations, wait intervals or polling loops

are needed to ensure that each calibration step completes before

issuing the next SPI command. Table 27 lists an example SPI

sequence for a particular case where the reference frequency (fCLK)

and ADC clock rate (FADC) are 200 MHz and FADC = 3200 MHz,

respectively. The remainder of this section describes the

configuration of the clock synthesizer in detail.

INTEGRATED

LOOP FILTER

TO Σ-∆ ADC

AND DIGITAL

N COUNTER

REG 0x2A1 (LSB)

REG 0x2A2 (MSB)

VDDQ

ENABLE CLK SYN

REG 0x2AO

÷2

REG 0x2A5

DIRECT RF

CLK OPTION

REG 0x2BB

VDDQ

VDDC

R-DIVIDER

CHARGE PUMP

REG 0x2AC

REG 0x2AD

REG 0x2BC

×2

fPFD =

10MHz TO 80MHz

CLK = 10MHz

TO 320MHz

INITIAL CAL

AUTOMATIC

LEVEL

CONTROL

CAL

REG 0x2AB

REG 0x2BC

VCO

5.9GHz TO 8.0GHz

REG 0x2AA

REG 0x2B7

Figure 99. CLK Synthesizer Block Diagram

AD6676EBZ 数据表(PDF) 35 Page - Analog Devices

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