AD6676EBZ datasheet(29/90 Pages) AD

29 / 90 page

Data Sheet

AD6676

Rev. D | Page 29 of 90



Surface mount inductors can be either wire-wound or

multilayer. The lower cost multilayer inductors typically

have quality factors below 20 that may have a slight impact

on the AD6676 NSD performance. Compare performance

between the two inductor types before making a decision to

select a lower cost multilayer type.



Because the voltage swing across the LC tank scales

proportionally with IDAC1FS, which sets PIN_0dBFS, a

reduction in IDAC1FS allows an inversely proportional

increase of LEXT to maintain a similar voltage swing. Note

that the minimum tuning capacitance from the internal

capacitor array along with any parasitic PCB capacitance

sets largest the LEXT as defined in Equation 3.

LMAX_TUNE = ((2π × FIF)2 × 7.1 pF)−1

(3)

The minimum capacitance contribution of the array can be up to

6.6 pF due to ±20 process variation. An additional 0.5 pF of PCB

parasitic capacitance is also included, thus a value of 7.1 pF is used.

Tie the two external inductors, LEXT, to the VDD2 supply via a

10 Ω resistor that includes a 0.1 μF decoupling capacitor, as

shown in Figure 93.

The following example highlights how LEXT can be determined

with the following application parameters: FIF = 150 MHz, FADC =

3.0 GHz and IDAC1FS = 4 mA. Referring to Figure 80, the LMAX

and LMIN range is from 20 nH to 70 nH. A value of 43 nH

represents 61% of LMAX and thus is suitable. Note that if the

IDAC1FS is reduced to 2 mA, this value can be increased to

86 nH because this value is below the absolute maximum.

Reduced PIN_0dBFS Operation via Scaling IDAC1FS

The PIN_0dBFS can be reduced by up to 12 dB because IDAC1FS is

adjustable over a 4 mA to 1 mA span as defined by Equation 4.

IDAC1FS = 4 mA × (IDAC1_FS/64)

(4)

where IDAC1_FS is the decimal equivalent of the value in

The LEXT value can be increased proportionally to any reduction

in IDAC1FS to maintain similar voltage swings across the LC tank.

The NSD and IMD performance are shown in Figure 81 and

Figure 82 for IDAC1FS settings of 4.0 mA, 2.0 mA, and 1.0 mA.

Figure 83 shows the STF response for each of these cases. Note

the following observations from this example:



With an IF of 300 MHz, the absolute maximum inductor is

39 nH; therefore, this inductor value is selected for both

IDAC1FS = 2.0 mA and 1.0 mA.



Reducing IDAC1FS from 4.0 mA to 2.0 mA and doubling

LEXT lowers the PIN_0dBFS by 6 dB but increases the

average in-band noise, IBN, by only 1.8 dB. The noise

figure of the ADC therefore improves by 4.2 dB.



Reducing IDAC1FS from 2.0 mA to 1.0 mA lowers the ADC

full scale by a further 6 dB and increases the average in-

band noise by only 4.6 dB. In this case, the noise figure

improvement is a modest 1.4 dB.



The swept IMD performance shows a degradation at

reduced IDAC1FS settings.



The STF response remains largely unaffected by reduced

IDAC1FS settings.

–145

–160

–155

–150

250

260

270

280

290

300

310

320

330

340

350

INPUT FREQUENCY (MHz)

IDAC1FS = 1mA, LEXT = 39nH

(IBN = –67.9dBFS)

IDAC1FS = 2mA, LEXT = 39nH

(IBN = –72.5dBFS)

IDAC1FS = 4mA, LEXT = 19nH

(IBN = –74.3dBFS)

Figure 81. NSD vs. IDAC1FS Setting with Decimate by 16, I/Q Output (IF =

300 MHz, BW = 100 MHz, FADC = 3.2 GHz)

–80

–98

–92

–86

–82

–94

–88

–84

–96

–90

250

260

270

280

290

300

310

320

330

340

350

FREQUENCY (MHz)

IDAC1FS = 4mA

(19nH)

IDAC1FS = 2mA

(39nH)

IDAC1FS = 1mA

(39nH)

Figure 82. Swept Dual-Tone IMD vs. IDAC1FS Setting with Decimate by 16, I/Q

Output, Dual Tones Set to −8 dBFS (IF = 300 MHz, BW = 100 MHz, FADC = 3.2 GHz)

0.5

–0.5

–0.1

0.2

0.4

–0.2

0.1

0.3

–0.3

–0.4

250

260

270

280

290

300

310

320

330

340

350

FREQUENCY (MHz)

IDAC1FS = 4mA

(19nH)

IDAC1FS = 2mA

(39nH)

IDAC1FS = 1mA

(39nH)

Figure 83. STF vs. IDAC1FS Setting with Decimate by 16, I/Q Output, Dual

Tones Set to −8 dBFS (IF = 300 MHz, BW = 100 MHz, FADC = 3.2 GHz)

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