AD6676EBZ datasheet(49/90 Pages) AD

49 / 90 page

Data Sheet

AD6676

Rev. D | Page 49 of 90

PHYSICAL LAYER INPUT/OUTPUTS

Digital Inputs

The AD6676 physical layer consists of consists of two digital

differential inputs, SYSREF± and SYNCINB±, whose equivalent

input circuits are shown in Figure 61 and Figure 64. These inputs

must be dc-coupled to their respective drivers because they are

or can be aperiodic. The SYNCINB± input is logic compliant to

both CMOS and LVDS via Register 0x1E7, Bit 2, with CMOS

being the default. Note that the SYNCINB± input includes an

internal 100 Ω termination resistor when LVDS is selected.

The optional SYSREF± input can be used for multichip

synchronization or establishing a repeatable latency between

the AD6676 and its host. The SYSREF± receiver circuit must be

disabled if not used (Register 0x1E7 = 0x04) to prevent

potential false triggering if the input pins are left open. The

SYSREF± input does not include an internal 100 Ω termination

resistor; thus, an external differential termination resistor must

be included if this input is used. The SYSREF± input is logic

complaint to LVPECL, LVDS, and CMOS.

Digital Outputs, Timing and Controls

The AD6676 physical layer consists of digital drivers that are

defined in the JEDEC Standard No. 204B (July 2011). These

CML drivers are powered up by default via Register 0x1E2. The

drivers utilize a dynamic 100 Ω internal termination to reduce

unwanted reflections. A 100 Ω differential termination resistor

at each receiver input results in a nominal 300 mV p-p swing at

the receiver.

The AD6676 JESD204B differential outputs can interface with

custom ASICs and FPGA receivers, providing superior switching

performance in noisy environments. Single point-to-point

network topologies are recommended with receiver inputs having

a nominal differential 100 Ω termination. The common mode

of the digital output automatically biases itself to half the VDDHSI

supply of 1.1 V (VCM = 0.55 V), thus making ac coupling the

preferred coupling method to the receiver logic as shown

Figure 122. DC coupling can be considered if the receiver device

shares the same VDDHSI supply and input common-mode range.

SERDOUTx+

VDDHSI

SERDOUTx–

OUTPUT SWING = 300mV

VCM = VDDHSI/2

100Ω

RECEIVER

100Ω

DIFFERENTIAL

TRACE PAIR

0.1µF

Figure 122. AC-Coupled Digital Output Termination Example

Timing errors caused by a degraded eye diagram at the receiver

input can often be attributed to poor far end termination or

differential trace routing. These potential error sources can be

reduced by using well controlled differential 100 Ω traces with

lengths below six inches that connect to receivers with integrated

differential 100 Ω resistors.

Figure 123, Figure 124, and Figure 125 show examples of the

digital output data eye, time interval error (TIE) jitter

histogram, and bathtub curve for one AD6676 lane running at

5.333 Gbps with Register 0x1EC set to 0xBD. The format of the

output data is twos complement by default. The output data

format can be changed via Register 0x146.

400

–400

–300

–200

–100

100

200

300

–150

150

100

–50

–100

TIME (ps)

EYE: ALL BITS, OFFSET: –0.0055

UIs: 4000; 1059998, TOTAL: 4000; 1059998

Figure 123. Digital Outputs Data Eye with External 100 Ω Terminations at

5.333 Gbps in Accordance to LV-OIF-11G-SR Mask

9000

8000

7000

6000

5000

4000

3000

2000

1000

–5

–4

–3

–2

–1

TIME (ps)

Figure 124. Digital Outputs Histogram with External 100 Ω Terminations at

5.333 Gbps

1–2

1–4

1–6

1–8

1–10

1–12

1–16

1–14

–0.5 –0.4 –0.3 –0.2 –0.1

0.5

0.4

0.3

0.2

0.1

UIs

Figure 125. Digital Outputs Data Bathtub with External 100 Ω Terminations

at 5.333 Gbps

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