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AD6676EBZ 数据表(PDF) 84 Page - Analog Devices |
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AD6676EBZ 数据表(HTML) 84 Page - Analog Devices |
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84 / 90 page  AD6676 Data Sheet Rev. D | Page 84 of 90 SYNCINB and SYSREF Control Register Address: 0x1E7, Reset: 0x00, Name: SYNCINB_CTRL Table 112. Bit Descriptions for SYNCB_CTRL Bits Bit Name Description Reset Access [7:4] RESERVED 0x0 RW 3 PD_SYSREF_RX Power down SYSREF receiver. 0x0 RW 2 LVDS_SYNCINB Use LVDS for SYNCINB. (0 = CMOS, 1 = LVDS differential with 100 Ω termination). 0x0 RW [1:0] RESERVED 0x0 RW Clock Synchronization Register Address: 0x1E8, Reset: 0x00, Name: MIX_CTRL Table 113. Bit Descriptions for MIX_CTRL Bits Bit Name Description Reset Access 7 RESERVED 0x0 RW 6 MIX_USE_2ND When used in conjunction with Bit 5, setting this bit causes the second SYSREF that is used to align the clocks to also be used to reset the mixer NCO phases. This bit does not self-clear. This bit is only active when Bit 2 is also active. 0x0 RW 5 MIX_NEXT Once set, only the next SYSREF pulse that is used to align the clock dividers is also used to reset the mixers NCO phases. This bit self clears after use. This bit is only active when Bit 1 is also active. 0x0 RWAC 4 MIX_ALL Any SYSREF that is used to align the clocks is also used to reset the mixers' NCO phases. This bit is only active when Bit 0 is also active. 0x0 RW 3 RESERVED 0x0 RW 2 USE_2ND_SYSREF When used in conjunction with Bit 1, setting this bit causes the second SYSREF to be used for alignment rather than the first. This bit does not self clear. 0x0 RW 1 NEXT_SYSREF Once set, only the next SYSREF pulse is used to align the clock dividers. This bit self- clears after the next SYSREF. 0x0 RWAC 0 ALL_SYSREF All SYSREF pulses are used to align the clock dividers. 0x0 RW LMFC Offset Register Address: 0x1E9, Reset: 0x00, Name: K_OFFSET Table 114. Bit Descriptions for K_OFFSET Bits Bit Name Description Reset Access [7:5] RESERVED 0x0 RW [4:0] K_OFFSET This register provides an offset that moves the position of the internal LMFC with respect to SYSREF. A larger value places the LMFC later in time. In units of frame periods. 0x00 RW SYSREF Window Register Address: 0x1EA, Reset: 0x00, Name: SYSREF Table 115. Bit Descriptions for SYSREF Bits Bit Name Description Reset Access [7:4] SYSREF_WIN_NEG SYSREF_WIN_NEG. Do not align clocks if SYSREF is no earlier than register value before its expected position. In units of 2/FADC. 0x0 RW [3:0] SYSREF_WIN_POS SYSREF_WIN_POS. Do not align clocks if SYSREF is no later than register value after its expected position. In units of 2/FADC. 0x0 RW |
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