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BCM5812

Advance Data Sheet

3/11/03

B roa dcom Co rpo rat ion

Page 42

Interrupt Processing

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5812-DS01-405-R

INTERRUPT PROCESSING

The BCM5812 generates an interrupt after completion of all packet descriptors for a particular MCR structure if the following

two conditions hold:

•

interrupts are enabled in the DMA control register (See Table 20 on page 59) (MCR1INT_EN enables interrupts for

symmetric operations pushed to MCR1@, and MCR2INT_EN enables interrupts for asymmetric and random number

operations pushed to MCR2@), and

•

the suppress interrupts bit in the MCR header word (See Table 1 on page 2) is zero. If this bit is set, the BCM5812 does

not issue a interrupt upon completion of processing of that MCR structure.

The DMA status register indicates interrupt status via the MCR1_INTR and MCR2_INTR bits, respectively. These bits must

be explicitly cleared by writing a 1 into the appropriate bit position.

The BCM5812 also generates an interrupt when either the MCR1@ or MCR2@ FIFO empties, as long as interrupts are

enabled for that FIFO. This mechanism is intended to deal with the condition where a sequence of MCRs are pushed with

interrupts suppressed. The DMA status register MCR1_ALL_EMPTY and MCR2_ALL_EMPTY bits indicate that their

respective interrupt has been issued. These are cleared by explicitly writing a 1 to the bit position, or by writing a 1 to the

MCR1_INTR or MCR2_INTR bit, respectively.

The BCM5812 generates an interrupt on DMA error if DMAERR_EN is set in the DMA control register. The DMA status

EXPORT CONTROL

The BCM5812 export control feature allows strong bulk cryptography to be disabled to facilitate products with retail export

classification. Export mode is controlled externally by whether the EXPORT pin (see Table 15 on page 47,

Table 16 on page 50, and Table 17 on page 53) is pulled high or low. If EXPORT is high, export mode is enabled, allowing

only 56-bit DES and disabling ARCFOUR, AES, and 3DES. If EXPORT is pulled low, all bulk cryptographic functionality is

enabled.

EXPORT is internally pulled high, and enabled by default.

ENDIAN CONSIDERATIONS

The BCM5812 is designed to work with both little endian and big endian host processors, in both standard and non-standard

PCI bus configurations.

The PCI bus is specified to work naturally with little endian host processors. Figure 38 on page 43 illustrates a typical little

endian 64-bit host processor bus configuration. In Figure 38 on page 43, the bytes are labelled from A to F, in the order that

they would be addressed by the host processor from memory (i.e., starting with the byte at the little end of the memory word).

Most big endian host processor systems are configured to swap bytes between the host processor or memory and the PCI

bus. Figure 39 on page 44 illustrates a typical big endian 64-bit host processor bus configuration. In Figure 39 on page 44,

the bytes are also labelled in the order that they would be addressed by the host processor from memory (i.e., starting from

the big end of the memory word).

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