5812-DS01-R datasheet(65/84 Pages) BOARDCOM

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Advance Data Sheet

BCM5812

3/11/03

B roa dcom Co rpo rat ion

Document

5812-DS01-405-R

PCI Configuration Registers

Page 57

Fast back to back capable status

22:23

RSVD

Reserved

Capability list

19:16

RSVD

0x00

Reserved

PCI Rev ID – 0x08

7:0

0x01/0xE1

Hardwired device revision identifier (0x01 for domestic version and 0xE1 for

export version)

PCI Class Code Register – 0x08

31:8

0x0B4000

Class code value (hardwired) – 0x0B4000 (processor class, coprocessor

subclass)

BIST, Header, Master Latency, PCI Cache Line – 0x0C

BIST capable, no BIST capability

BIST start, writing has no effect

29:24

0x00

BIST register, Not supported in BCM5812. Default to 0x00.

23:16

0x00

Header type = 0, single function

15:10

0x0C

Master latency timer. The value in this register defines the maximum length of the

current burst should the PCI arbiter logic remove the GNT signal from the

BCM5812 device. This value is ignored as long as the GNT signal remains

asserted to the BCM5812. Once GNT is removed, the latency timer limit is

immediately applied. This register can be programmed with values from 0x00 to

0xfc. Only the six most significant bits are implemented (two LSBs are hardwired

to 0). A value of zero would cause the BCM5812 to perform one data phase.

9:8

0x00

7:0

0x00

Cache line size. The value in this register determines what types of PCI bus

master read cycles are generated by the BCM5812 device. When the intended

read burst is smaller than a full cacheline and is completely contained within a

single cache line, a MEM_READ cycle is generated. When the intended read

burst is exactly one full cacheline or crosses only one cacheline boundary, a

MEM_READ_LINE cycle is generated. When the intended burst is exactly two

full cachelines or crosses multiple cache line boundaries, a

MEM_READ_MULTIPLE cycle is used. Setting this register to zero inhibits the

BCM5812 from generating any MEM_READ_LINE or MEM_READ_MULTIPLE

cycles.

PCI Memory BAR – 0x10

31:16

0xFFFF

Memory Base Address Register (upper), 64 KB region, non-prefetchable,

relocate in 32-bit space only.

15:0

0x0000

Memory Base Address Register (lower), 64 KB region, non-prefetchable,

relocate in 32-bit space only.

Subsystem ID, Subsystem Vendor ID – 0x2C

31:16

0x0200 /

0x0500

Subsystem ID

• BCM5812-200 = 0x0200

• BCM5812-500 = 0x0500

15:0

0x14E4

Subsystem Vendor ID (Broadcom PCISIG ID)

Table 19: PCI Configuration Register Bit Fields (Cont.)

Bits

Access

Reset

Purpose

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