5812-DS01-R datasheet(68/84 Pages) BOARDCOM

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BCM5812

Advance Data Sheet

3/11/03

B roa dcom Co rpo rat ion

Page 60

DMA Control and Status Registers

Document

5812-DS01-405-R

MCR2INT_EN - Enable interrupt per MCR for MCR2@. An interrupt is generated every

time an entire MCR completes processing. This is the preferred operational mode. Resets

to 0.

MCR1INT_EN - Enable interrupt per MCR for MCR1@. An interrupt is generated every

time an entire MCR completes processing. This is the preferred operational mode. Resets

to 0.

RSVD

Reserved

LE_CRYPTONET - Software structures in DMA memory (as seen from the PCI bus) are

in:

• 1 = little endian format.

• 0 = big endian format.

BCM5812 uses this bit to correctly interpret the appropriate structures in DMA memory

during the BCM5812 bus master operations. Optimally, this bit configuration should match

the endianess of the host CPU.

NORMAL_PCI:

• 1 = Normal PCI mode.

• 0 = Swapped PCI mode; all PCI bus master memory data is internally byte-swapped by

the BCM5812.

Used for testing. This bit should normally be set to 1.

DMAERR_EN - Enable interrupt upon DMA master access error.

RSVD

Reserved

RNG_MODE

• 0 = 1 bit random number per one slow clock cycle.

• 1 = 1 bit random number per two slow clock cycles

Modulus Normalization

• 0 = Modulus normalization is done by BCM5812. Software must not perform modulus

normalization function.

• 1 = Modulus normalization must be done by software.

Provided for backwards compatibility. Should always be 0.

21:17

RSVD

Reserved

DMA Master Write Burst Size Select

• 0 = Master write burst size is 128 bytes.

• 1 = Master write burst size is 240 bytes.

15:0

RSVD

Reserved

DMA Status – 0x08

Master access in progress. Resets to 0.

MCR1_FULL flag = Master command address register is full. When this flag is 1, the CPU

must not write to the MCR1@ register. When this flag is 0, the CPU may write a value to

the MCR1@ register to request processing of a master command structure. Resets to 0.

MCR1_INTR = Completion interrupt status of per-MCR interrupt for MCR1@. Cleared by

writing a 1 to this bit position. This bit accurately reflects processing status even if the

corresponding interrupt bit is disabled (in which case a PCI interrupt is not generated).

This bit is sticky until cleared explicitly. Resets to 0.

Table 21: DMA Control and Status Registers (Cont.)

Bits

Access

Reset

Purpose

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