5812-DS01-R datasheet(9/84 Pages) BOARDCOM

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Advance Data Sheet

BCM5812

3/11/03

B roa dcom Co rpo rat ion

Document

5812-DS01-405-R

Functional Description

Page 1

Secti on 1: Fu nction al Descri p ti on

OVERVIEW

The BCM5812 is a low-cost, general purpose security processor that incorporates specialized features for IPsec, IKE, SSL,

and TLS protocol processing. The BCM5812 is a member of Broadcom’s Security Processor family and fully software

compatible with the higher performance BCM5821 and BCM5820.

The BCM5812 provides bulk cryptographic acceleration for the 3DES, DES, AES, and ARCFOUR symmetric encryption

algorithms, for the SHA-1 and MD5 hash algorithms, and for the HMAC-SHA-1 and HMAC-MD5 keyed authentication

algorithms. It provides public key acceleration for the RSA, DSA, and Diffie-Hellman asymmetric algorithms, as well as basic

modular math functions. The BCM5812 provides a true random number generator, and can use it to generate on-chip

random values for Diffie-Hellman key generation and DSA signatures.

The BCM5812 provides combined encryption and HMAC authentication for single pass IPsec processing. It also provides

the SSL MAC and TLS HMAC functions needed for SSL and TLS record layer processing, respectively.

Bulk encryption and public key processing are performed in separate processing functions within the BCM5812. These share

a common bus interface, but are otherwise independent. The BCM5812 can thus complete multiple bulk encryption

operations while simultaneously executing a relatively slower public key operation, without having to stall bulk processing.

The BCM5812 is ideal as a single-chip, low-cost security solution for both embedded systems and add-in option modules.

It interfaces directly to the PCI bus with no need for additional interface logic, operates without external memory, and can

derive its clock from the PCI bus. It supports all of the algorithms needed for IPsec, IKE, SSL, and TLS security protocols,

and used as well by many other protocols, such as Secure RTP.

PROGRAMMING INTERFACE

The BCM5812 is a bus master PCI device that uses programming structures designed to facilitate pre-fetching for high

device utilization. These structures are built by the host processor in main memory and accessed by the BCM5812 using

DMA, as diagrammed in Figure 2.

The BCM5812 is controlled using a block of five Control and Status Registers (CSR). The host processor maps the CSR

block into PCI memory space, usually at system initialization, by writing the start address of the CSR block into BCM5812

PCI configuration register BAR0. Host software accesses the BCM5812 CSR block by doing PCI memory (slave) reads and

writes starting at this address.

The main programming structure is the Master Command Record (MCR), shown in Figure 3 on page 3. The MCR consists

of a header word followed by an array of one or more packet descriptors. A single MCR can accommodate up to 65535

packet descriptors. Table 1 on page 2 shows the fields in the header word that would be set by the host processor before

giving the MCR to the BCM5812.

The host software gives an MCR to the BCM5812 by writing the address of the MCR structure to either the MCR1@ or

MCR2@ CSR, depending on the type of operation (see Table 3 on page 5). The BCM5812 provides a four-level FIFO

behind MCR1@ and MCR2@, which permits the host software to push up to four MCR addresses at a time to each. The

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