5812-DS01-R datasheet(63/84 Pages) BOARDCOM

63 / 84 page

Advance Data Sheet

BCM5812

3/11/03

B roa dcom Co rpo rat ion

Document

5812-DS01-405-R

Page 55

Sec t ion 3: Re gister D e ta ils

The BCM5812 registers are divided into two categories.

PCI configuration registers implement control and status information that is specific to the PCI bus, as well as registers

required by the PCI specification rev. 2.2.

DMA control and status registers pertain to master command, data, and command context fetch and write back

operations.

Unused or reserved bits are initialized to zero. Unused bits should be written as zeroes. The following mnemonics are used

to describe the types of access allowed for each register bit:

•

RW – bit is read/write

•

WO – bit is write only

•

RO – read only bit (i.e. status flag)

•

RSVD – reserved bit, ignore upon read, write 0 upon write

A value of X upon reset means that the state of the register is undefined and should not be relied upon after a reset occurs.

PCI CONFIGURATION REGISTERS

The BCM5812 provides PCI 2.2 compliant configuration space registers as shown in Table 18. In addition, the BCM5812

uses PCI Memory as configured in BAR0 for all slave control and status registers (CSRs). The registers use a total memory

space of 64 KB in one memory BAR region. This region is non-prefetchable, and must be relocated only in 32-bit space.

Configuration registers that are not shown in Table 18 are reserved.

The various registers within PCI configuration space are shown in Table 19.

An optional serial EEPROM allows the following PCI register parameters to be modified:

Table 18: PCI Configuration Registers

Offset

bits

16 15

bits

0x00

Device ID

Vendor ID

0x04

Status

Command

0x08

Class code

Rev ID

0x0C

BIST

Header Type

Master Latency Timer

Cache line Size

0x10

Memory BAR0

0x2C

Subsystem ID

Subsystem Vendor ID

0x34

Reserved

Capabilities Pointer

0x3C

MAX_LAT

MIN_GNT

Interrupt Pin

Interrupt Line

0x40

Reserved

Retry Timeout

TRDY Timeout

0x48

Power Management Capabilities

Next Capability Pointer

(End Of List)

Power Management

Capability ID

0x4c

Reserved

Power Management Control/Status

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