ST10F166 datasheet(52/62 Pages) STMICROELECTRONICS

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ST10F166

AC Characteristics (Cont’d)

Demultiplexed Bus for the ST10F166-16

CC =5 V

± 10 %;

SS =0V

A = 0 to +70

°C

L (for Port 0, Port 1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF

ALE cycle time = 4 TCL + 2t

A +tC +tF (100 ns at 20-MHz CPU clock without wait-

states)

Parameter

Symbol

CPU Clock = 16 MHz

Duty cycle 0.4 to 0.6

Variable CPU Clock

1/CLP = 1 to 20 MHz

Unit

min.

max.

min.

max.

ALE high time

15 + t

–

TCLmin -10

–ns

Address setup to ALE

t6CC

10 + t

–

TCLmin -15

–ns

ALE falling edge to RD, WR

(with RW-delay)

t8CC

15 + t

–

TCLmin -10

–ns

ALE falling edge to RD, WR

(no RW-delay)

t9 CC

-10 + t

–

-10

–ns

RD, WR low time

(with RW-delay)

12 CC

52.5 + t

–

CLP - 10

–ns

RD, WR low time

(no RW-delay)

13 CC

77.5 + t

–

CLP+TCLmin

-10 + t

–ns

RD to valid data in

(with RW-delay)

14 SR

–

47.5 + t

–

CLP - 20

RD to valid data in

(no RW-delay)

15 SR

–

72.5 + t

–

CLP+TCLmin

-20 + t

ALE low to valid data in

–

72.5

A +tC

–

CLP+TCLmin

-20 + t

A +tC

Address to valid data in

–

100

+2t

A +tC

–

2CLP - 25

+2t

A +tC

Data hold after RD

rising edge

–

Data float after RD rising edge

(with RW-delay)

–

47.5 + t

–

CLP - 15 + t

Data float after RD rising edge

(no RW-delay)

–

15 + t

–

TCLmin -10

Data valid to WR

47.5 + t

–

CLP - 15 + t

–ns

Data hold after WR

15 + t

–

TCLmin -10

–ns

ALE rising edge after RD, WR

-10 + t

–

-10 + t

–ns

Address hold after RD, WR

0 + t

–0 + t

–ns

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