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ST10F166 数据表(PDF) 57 Page - STMicroelectronics |
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ST10F166 数据表(HTML) 57 Page - STMicroelectronics |
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57 / 62 page ![]() ST10F166 57/62 AC Characteristics (Cont’d) CLKOUT and READY for ST10F166, V CC =5 V ± 10 %; V SS =0V T A = 0 to +70 °C C L (for Port 0, Port 1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF Notes: 1) These timings are given for test purposes only, in order to assure recognition at a specific clock edge. 2) Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This adds even more time for deactivating READY. Parameter Symbol Max. CPU Clock = 20 MHz Variable CPU Clock 1/2TCL = 1 to 20 MHz Unit min. max. min. max. CLKOUT cycle time t 29 CC 50 50 2TCL 2TCL ns CLKOUT high time t30CC 15 – TCL – 10 – ns CLKOUT low time t31CC 15 – TCL – 10 – ns CLKOUT rise time t 32 CC – 5 – 5 ns CLKOUT fall time t 33 CC – 5 – 5 ns CLKOUT rising edge to ALE falling edge t 34 CC 0 + t A 10 + t A 0+ t A 10 + t A ns Synchronous READY setup time to CLKOUT t 35 SR 10 – 10 – ns Synchronous READY hold time after CLKOUT t 36 SR 10 – 10 – ns Asynchronous READY low time t 37 SR 65 – 2TCL + 15 – ns Asynchronous READY setup time 1) t58SR 20 – 20 – ns Asynchronous READY hold time 1) t59SR 0 – 0 – ns Async. READY hold time after RD, WR high (Demul- tiplexed Bus) 2) t60SR 0 0 +2t A +tF 2) 0 TCL - 25 +2t A +tF 2) ns |
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