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ST10F166 数据表(PDF) 60 Page - STMicroelectronics |
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ST10F166 数据表(HTML) 60 Page - STMicroelectronics |
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60 / 62 page ![]() 60/62 ST10F166 AC Characteristics (Cont’d) External Bus Arbitration V CC =5 V ± 10 %; V SS =0V T A = 0 to +70 °C for ST10R165 C L (for Port 0, Port 1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF Figure 24. External Bus Arbitration, Releasing the Bus Notes: 1) The ST10R165 will complete the currently running bus cycle before granting bus access. 2) This is the first possibility for BREQ to get active. Parameter Symbol Max. CPU Clock =20 MHz Variable CPU Clock 1/2TCL = 1 to 20 MHz Unit min. max. min. max. HOLD input setup time to CLKOUT t 61 SR 20 – 20 – ns CLKOUT to HLDA high or BREQ low delay t 62 CC – 30 – 30 ns CLKOUT to HLDA low or BREQ high delay t 63 CC – 30 – 30 ns Other signals release t66CC – 25 – 25 ns Other signals drive t67CC -5 35 -5 35 ns CLKOUT HOLD t 61 HLDA t 63 Other Signals t 66 1) 1) 2) BREQ t 62 |
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