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ST10F166 数据表(PDF) 28 Page - STMicroelectronics |
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ST10F166 数据表(HTML) 28 Page - STMicroelectronics |
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28 / 62 page ![]() 28/62 ST10F166 15 SOFTWARE DESCRIPTION Addressing Modes The ST10F166 offers different powerful addressing modes to facilitate rapid access on word, byte and bit data, or to specify the destination address of a branch instruc- tion. The addressing modes are subdivided in six different categories as follows. Short addressing modes: an implicit base offset address is used to specify a phys- ical 18-bit address. EA = Base Address + k Short Address. k= 1 or2 EA = Effective Address This mode allows direct access to any GPR or SFR and any word in the bit-address- able memory space. (in case of a byte operation on an SFR, only the low byte can be accessed via ‘reg’). Long addressing modes: one of the four DPP registers, selected by bit 15 and 14 of the 16-bit address, is used to specify a physical 18-bit address. EA = Contents of DPPi + Page Offset Address i: specified by bit 15, 14 of the 16 bit address. Page Offset Address: bit 13 to 0 of the 16 bit address. In this mode, any word or byte data within the entire memory space can be accessed directly . Word accesses may not be performed on odd byte addresses, otherwise a hardware trap will occur. Indirect addressing modes: a 16-bit long address is specified indirectly by the con- tents of a word GPR which is specified directly by a short address. Any word GPR can be used, except for arithmetic, logical and compare instructions, where only R0 to R3 are allowed. There are also certain modes which allow decrementing or incrementing the indirect address pointers by a data-type-dependent value. Long Address = [GPR Address] + Constant EA = Contents of DPPi + Page Offset Address i: specified by bit 15, 14 of the Long Address. Page Offset Address: bit 13 to 0 of the long address Long Address Long Address bit15,14 specify i bit 13 to 0 |
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