ST10F166 datasheet(22/62 Pages) STMICROELECTRONICS

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ST10F166

11 WATCHDOG TIMER

The Watchdog Timer of the ST10F166 represents one of the fail-safe mechanisms

which have been implemented to prevent the controller from malfunctioning for longer

periods of time.

The Watchdog Timer of the ST10F166 is always enabled after a reset of the chip, and

can only be disabled in the time interval until the EINIT (end of initialization) instruc-

tion has been executed. Thus, the chip’s start-up procedure is always monitored.

When the software has been designed to service the Watchdog Timer before it over-

flows, the Watchdog Timer times out if the program does not progress properly due to

hardware or software related failures. When the Watchdog Timer overflows, it gener-

ates an internal hardware reset and pulls the RSTOUT pin low in order to allow exter-

nal hardware components to reset.

The Watchdog Timer of the ST10F166 is a 16-bit timer which can either be clocked

with fosc/4 or fosc/256. The high byte of the Watchdog Timer register can be set to a

prespecified reload value (stored in WDTREL) in order to allow further variation of the

monitored time interval. Each time it is serviced by the application software, the high

byte of the Watchdog Timer is reloaded. Thus, time intervals between 25

µs and 420

ms can be monitored (@fosc = 40 MHz). The default Watch-dog Timer interval after

reset is 6.55 ms.

12 PARALLEL PORTS

The ST10F166 provides 76 I/O lines which are organized into four 16-bit I/O ports

(Port 0 through 3), one 2-bit I/O port (Port 4), and one 10-bit input port (Port 5). All port

lines are bit addressable, and all lines of Port 0 through 4 are individually bit program-

mable as inputs or outputs via direction registers. The I/O ports are true bidirectional

ports which are switched to the high impedance state when configured as inputs. Dur-

ing the internal reset, all port pins are configured as inputs.

Each port line has one programmable alternate input or output function associated

with it. Ports 0 and 1 may be used as address and data lines when accessing external

memory, while Port 4 outputs the additional segment address bits A16 and A17 in

systems where segmentation is enabled to access more than 64 Kbytes of memory.

Port 2 is associated with the capture inputs/compare outputs of the CAPCOM unit,

and Port 3 includes alternate functions of timers, serial interfaces, optional bus con-

trol signals (WR, BHE, READY), and the system clock output (CLKOUT). Port 5 is

used for the analog input channels to the A/D converter. When none of the alternate

functions is not used, the respective port line may be used as general purpose I/O

line.

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