ST10F166 datasheet(21/62 Pages) STMICROELECTRONICS

21 / 62 page

ST10F166

21/62

10 SERIAL CHANNELS

Serial communication with other microcontrollers, processors, terminals, or external

peripheral components is provided by two serial interfaces with identical functionality,

Serial Channel 0 (ASC0) and Serial Channel 1 (ASC1).

They support full-duplex asynchronous communication up to 625 Kbaud and half-du-

plex synchronous communication up to 2.5 Mbaud.

Two dedicated baud rate generators allow to set up all standard baud rates without

oscillator tuning. For transmission, reception, and erroneous reception 3 separate in-

terrupt vectors are provided for each serial channel.

In the synchronous mode, one data byte is transmitted or received synchronously to

a shift clock which is generated by the ST10F166. In the asynchronous mode, an 8-

or 9-bit data frame is transmitted or received, preceded by a start bit and terminated

by one or two stop bits. For multiprocessor communication, a mechanism to distin-

guish address from data bytes has been included (8-bit data + wake up bit mode),

and a loop back option is available for testing purposes.

A number of optional hardware error detection capabilities has been included to in-

crease the reliability of data transfers. A parity bit can automatically be generated on

transmission or be checked on reception. Framing error detection allows to recognize

data frames with missing stop bits. An overrun error will be generated if the last char-

acter received has not been read out of the receive buffer register at the time the re-

ception of a new character is complete.

ST10F166 数据表(PDF) 21 Page - STMicroelectronics