 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
ST10F166 数据表(PDF) 42 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
ST10F166 数据表(HTML) 42 Page - STMicroelectronics |
|
|
42 / 62 page  42/62 ST10F166 18.5 Testing Waveforms Figure 11. Input Output Waveforms Figure 12. Float Waveforms 18.6 Memory Cycle Variables The timing tables below use three variables which are derived from registers SY- SCON and BUSCON1 and represent the special characteristics of the programmed memory cycle. The following table describes, how these variables are to be comput- ed. AC inputs during testing are driven at 2.4 V for a logic ‘1’ and 0.4 V for a logic ‘0’. Timing measurements are made at V IH min for a logic ‘1’ and VIL max for a logic ‘0’. For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs, but begins to float when a100 mV change from the loaded V OH/VOL level occurs (I OH/IOL = 20 mA). Description Symbol Values ALE Extension t A TCL * <ALECTL> Memory Cycle Time Waitstates t C 2TCL * (15 - <MCTC>) Memory Tristate Time tF 2TCL * (1 - <MTTC>) |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
