ST10F166 datasheet(58/62 Pages) STMICROELECTRONICS

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ST10F166

AC Characteristics (Cont’d)

CLKOUT and READY for ST10F166-16

CC =5 V

± 10 %;

SS =0V

A = 0 to +70

°C

L (for Port 0, Port 1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF

Notes:

1) These timings are given for test purposes only, in order to assure recognition at a specific clock edge.

2) Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values.

This adds even more time for deactivating READY.

The 2tA refer to the next following bus cycle.

Parameter

Symbol

CPU Clock = 16 MHz

Duty cycle 0.4 to 0.6

Variable CPU Clock

1/CLP = 1 to 20 MHz

Unit

min.

max.

min.

max.

CLKOUT cycle time

62.5

CLP

CLKOUT high time

t30CC

–

TCLmin –10

–

CLKOUT low time

t31CC

–

TCLmin –10

–

CLKOUT rise time

–

CLKOUT fall time

–

CLKOUT rising edge to

ALE falling edge

0 + t

10 + t

0+ t

10 + t

Synchronous READY

setup time to CLKOUT

–

Synchronous READY

hold time after CLKOUT

–

Asynchronous READY

low time

77.5

–

CLP + 15

–

Asynchronous READY

setup time 1)

t58SR

–

Asynchronous READY

hold time 1)

t59SR

–

Async. READY hold time

after RD, WR high (Demul-

tiplexed Bus)

t60SR

+2t

A +tF

TCL - 25

+2t

A +tF

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