STV0974 datasheet(55/69 Pages) STMICROELECTRONICS

55 / 69 page

Electrical characteristics

STV0974

55/61

5.5

AC electrical characteristics

5.5.1

CLK

5.5.2

I2C slave timing

Table 38: CLK electrical characteristics (

Figure 30)

Symbol

Parameter

Min.

Typ.

Max.

Unit

VCDC

DC coupled square wave voltage

1.7

1.8

1.9

Vp-p

fCLK

Clock frequency input

6.5

MHz

Figure 30: CLK electrical characteristics

Table 39: I2C slave timing (

Figure 31)

Symbol

Parameter

Min.

Typ.

Max.

Unit

fSCL

SCL clock frequency

400

kHz

tLOW

Clock pulse width low

1.3

µs

tHIGH

Clock pulse width high

0.6

µs

tSP

Pulse width of spikes which are suppressed by the

input filter

tBUF

Bus free time between transmissions

1.3

µs

tHD.STA

Start hold time

0.6

µs

tSU.STA

Start set-up time

0.6

µs

tHD.DAT

Data in hold time

0.15

0.9

µs

tSU.DAT

Data in set-up time

100

SCL / SDA rise timea

a. Measured from 0.1 to 0.9 or 0.9 to 0.1 VDD and with 4.7 k pull-up resistor and 100pF maximum

capacitance on both SDA and SCL.

300

SCL / SDA fall timea

300

tSU.STO

Stop set-up time

0.6

µs

tDH

Data out hold-time

0.6

0.9

µs

1/fCLK

VCDC

STV0974 数据表(PDF) 55 Page - STMicroelectronics

STV0974 数据表(HTML) 55 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69

数据表下载