STV0974 datasheet(22/69 Pages) STMICROELECTRONICS

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STV0974

Functional description

Status Register (SR)

The status register is an 8-bit read-only direct register holding all pending requests from the camera

subsystem.

Table 10: Status Register

Bits

Name

Type

Description

IRQ

Interrupt Request: IRQ is set when at least one of the interrupt sources is set, and the

corresponding bit mask is set.

Reserved.

EOF

End Of Frame: EOF is set by the falling edge of VENV

(output image vertical envelope).

SOF is cleared by writing ICLR bit 5.

SOF

Start Of Frame: SOF is set by the rising edge of VENV (output image vertical

envelope).

SOF is cleared by writing ICLR bit 4.

MCI

Micro-Core Interrupt: MCI is set by the micro-core to alert the host of the occurrence

of an internal event (status update, error, etc.…).

MCI is cleared by writing ICLR bit 3.

FERR

FIFO Error: FERR is set by the FIFO controller if a FIFO overflow occurs, or if the

FIFO is not empty when cleared at the start of frame.

FERR is cleared by writing ICLR bit 2.

FRDY

FIFO Ready: This bit indicates that the number of valid bytes in the FIFO is greater

than or equal to the FIFO threshold value, i.e:

FRDY = (Nbytes

≥ threshold)

During the inter-frame period, ‘threshold’ is forced to ‘1’ to flush the FIFO; otherwise,

‘threshold’ is determined by FHTR.

FRDY is level sensitive, i.e. it can be cleared only by reading FIFO.

RDY

Ready: This bit indicates the state of the access request between the host and the

STV0974:

0 = Register access in progress,

1 = AR, DR and DW can be accessed by the host.

For a read access, RDY is cleared upon host write to AR (MSB); it is set by the micro-

core when DR is updated with the register data.

For a write access, RDY is cleared upon host write to DW; it is set by the micro-core

when the internal register is updated.

Note: RDY is high when AR points to the interface indirect registers.

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