STV0974 datasheet(26/69 Pages) STMICROELECTRONICS

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STV0974

Functional description

FIFO Count Register (FCNT)

FCNT is a read-only 16-bit register, returning the current number of bytes available in the FIFO.

4.5.5

Image transfer operation

Interrupt controlled transfer

The STV0974 generates interrupts by asserting the IRQ signal. The host interrupt handler performs

the following operations:

1 Read the status register SR to determine if the STV0974 is the interrupting device (IRQ bit) and

detect the active interrupt sources.

2 Acknowledge pending interrupts by writing ICLR.

3 Service the interrupt source(s), i.e. for example:

MCI: read micro-core status and error registers (camera control channel).

SOF: trigger frame synchronous task.

FF: empty the FIFO by reading 16-byte blocks (camera image data channel).

RDY: read DR for a pending read, write next AR (low-level byte transfer).

4 Interrupts can be disabled through IMASK.

DMA controlled transfer

The STV0974 supports DMA operation for image data transfer: the DRQ output signal is used to

trigger a DMA burst read transfer from peripheral to memory. A full image transfer under DMA

executes as follows:

1 The STV0974 is initialized: DMA burst size, FIFO is cleared.

2 DRQ is asserted when the image FIFO threshold is reached or exceeded.

3 The DMA controller starts performing the burst read transfer consisting of 8, 16 or 32 byte reads.

Table 20: FIFO Count Register

Bits

Name

Type

Description

[15:0]

FCNT

Number of bytes available in the image data FIFO.

Figure 12: Full image transfer under DMA

12n

IRQ

FIFO

Read

DRQ

(POL = 0)

FIFO level

threshold

Frame

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