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STV0974 数据表(PDF) 29 Page - STMicroelectronics |
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STV0974 数据表(HTML) 29 Page - STMicroelectronics |
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29 / 69 page ![]() Functional description STV0974 29/61 4.6.3 HSYNC and VSYNC video synchronization HSYNC and VSYNC synchronization timing is shown in the Figure 15. 4.6.4 Data timing The YUV timing and the 3 RGB timings are also represented on Figure 16, with the associated qualifying HCLK clock. Figure 15: Horizontal and vertical synchronization Figure 16: Timings with associated qualifying clocks EAV Blanking Blanking Active Active lines HSYNC VSYNC V=0 V=1 H=1 H =0 SAV Yn Un,n+1 Yn+1 Vn,n+1 YCbCr HCLK Data[7:0] HCLK Data[7:0] RGB565 HCLK Data[7:0] RGB332 Un+2,n+3 RGB444 Pix0_lsb Pix0_msb Pix2_lsb Pix2_msb Pix3_lsb Pix0 Pix1 Pix2 |
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