STV0974 datasheet(24/69 Pages) STMICROELECTRONICS

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STV0974

Functional description

FIFO Register (FIFO)

FIFO is a read-only register. When read, FIFO returns the least recent byte from the image data

FIFO, decrements the byte count and releases the FIFO interrupt if the count is lower than the

threshold. Reading from an empty FIFO returns the last valid byte read.

The image data FIFO is cleared at the beginning of VENV, the image vertical envelope. If the FIFO

is not empty, its contents are discarded and the FERR flag is raised in the status register SR. New

image data start to fill in the FIFO. If an overflow occurs during VENV, the FERR flag is also raised

in SR; FERR can be cleared through ICLR.

Microprocessor Interface Control Register (MICR)

MICR controls and configures the image data transfer.

Table 14: FIFO register

Bits

Name

Type

Description

[7:0]

FIFO

Image data byte (uncompressed or compressed).

Table 15: Microprocessor Interface Control Register

Bits

Name

Type

Description

[7:6]

Reserved.

IRQPOL

IRQ pin polarity:

0 = active high

1 = active low

DRQPOL

DRQ pin polarity:

0 = active high

1 = active low

[3:2]

BSIZE

DMA burst size and enable:

00 = DMA operation disabled, DRQ pin is high impedance

01 = 8-byte burst

10 = 16-byte burst

11 = 32-byte burst

Reserved, read as zero, ignored upon write

CLR

Clear FIFO (Write Only, read as 0):

0 = No action

1 = Reset FIFO to empty state

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