STV0974 datasheet(56/69 Pages) STMICROELECTRONICS

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STV0974

Electrical characteristics

5.5.3

I2C master timing

Figure 31: I2C slave timing

Table 40: I2C master timing

Symbol

Parameter

Min.

Typ.

Max.

Unit

fSCL

MSCL clock frequency a

a. 200 kHz recommended through system patch. Please contact ST for details.

200

400

kHz

tLOW

Clock pulse width low

1.1

µs

tHIGH

Clock pulse width high

0.6

µs

tBUF

Bus free time between transmissions

1.3

µs

tHD.STA

Start hold time

0.6

µs

tSU.STA

Start set-up time

0.6

µs

tHD.DAT

Data in hold time

0.15

0.9

µs

tSU.DAT

Data in set-up time

100

MSCL / MSDA rise time b

b. Measured from 0.1 to 0.9 or 0.9 to 0.1 VDD and with 4.7 k pull-up resistor and 100pF maximum

capacitance on both MSDA and MSCL.

300

MSCL / MSDA fall time b

300

tSU.STO

Stop set-up time

0.6

µs

tDH

Data out hold-time

0.6

0.9

µs

Stop

Start

tBUF

tLOW

tHIGH

tHD.STA

tHD.DAT

tSU.DAT

tSU.STA

tHD.STA

tSU.STO

SCL

SDA

Start

Stop

Note:

tDH is the same timing as tHD.DAT. tDH is a value driven by the STV0974. tHD.DAT is the value

when the host is driving.

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