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STV0974 数据表(PDF) 64 Page - STMicroelectronics |
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STV0974 数据表(HTML) 64 Page - STMicroelectronics |
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64 / 69 page  64/61 STV0974 PCB layout guide lines for the STV0974 and VS6552 7 PCB layout guide lines for the STV0974 and VS6552 Normal good PCB design practice should be observed for the layout of the STV0974. Power and ground planes should be used to supply power to STV0974. The high speed subLVDS signal pairs (PCLKP,PCLKN) and (PDATAP,PDATAN) should be routed as balanced transmissions lines with a characteristic balanced impedance of between 80 to 120 Ω. The two traces in the signal pair should be routed together and should be matched in length to within +/-3mm. The pairs of balanced line traces should be matched in length to within +/- 10mm. To save components, 100 Ω termination resistors are embedded in the high speed subLVDS signal pairs (PCLKP/PCLKN) and (PDATAP/PDATAN) of the STV0974. All passive components for the STV0974 should be placed in close proximity to the device, including the decoupling capacitors. The decoupling capacitors for the VS6552 should be placed close to the sensor. |
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