XRT83SL34IV datasheet(13/80 Pages) EXAR

13 / 80 page

XRT83SL34

QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.0.8

A[6]

A[5]

A[4]

A[3]

A[2]

A[1]

A[0]

JASEL1

JASEL0

EQC4

EQC3

EQC2

EQC1

EQC0

Microprocessor Address Pins - Host mode:

Microprocessor Interface Address Bus[6]

Microprocessor Interface Address Bus[5]

Microprocessor Interface Address Bus[4]

Microprocessor Interface Address Bus[3]

Microprocessor Interface Address Bus[2]

Microprocessor Interface Address Bus[1]

Microprocessor Interface Address Bus[0]

Jitter Attenuator Select Pins - Hardware Mode

Jitter Attenuator select pin 1

Jitter Attenuatore select pin 0

See “Jitter Attenuator” on page 11.

Equalizer Control Pins - Hardware Mode

Equalizer Control Input pin 4

Equalizer Control Input pin 3

Equalizer Control Input pin 2

Equalizer Control Input pin 1

Equalizer Control Input pin 0

Pins EQC[4:0] select the Receive Equalizer and Transmitter Line Build Out.

See “Alarm Function//Redundancy Support” on page 13.

NOTE: Internally pulled “Low” with a 50k

Ω resistor.

INT

TRATIO

119

Interrupt Output - Host Mode

This pin goes “Low” to indicate an alarm condition has occurred within the

device. Interrupt generation can be globally disabled by setting the GIE bit to

"0" in the command control register.

Transmitter Transformer Ratio Select - Hardware mode

The function of this pin is to select the transmitter transformer ratio. See

“Alarm Function//Redundancy Support” on page 13.

NOTE: This pin is an open drain output and requires an external 10k

Ω pull-

up resistor.

SIGNAL NAME

PIN #TYPE

DESCRIPTION

XRT83SL34IV 数据表(PDF) 13 Page - Exar Corporation

XRT83SL34IV 数据表(HTML) 13 Page - Exar Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

数据表下载