XRT83SL34IV datasheet(49/80 Pages) EXAR

49 / 80 page

XRT83SL34

QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.0.8

TABLE 20: MICROPROCESSOR REGISTER #1, BIT DESCRIPTION

0000001

0010001

0100001

0110001

CHANNEL_n

CHANNEL_0

CHANNEL_1

CHANNEL_2

CHANNEL_3

FUNCTION

TYPE

RESET

VALUE

BIT #NAME

RXTSEL_n

Receiver Termination Select: In Host mode, this bit is used

to select between the internal and external line termination

modes for the receiver according to the following table;

R/W

TXTSEL_n

Transmit Termination Select: In Host mode, this bit is used

to select between the internal and external line termination

modes for the transmitter according to the following table;

R/W

TERSEL1_n

Termination Impedance Select1:

In Host mode and in internal termination mode, (TXTSEL = “1”

and RXTSEL = “1”) TERSEL[1:0] control the transmit and

receive termination impedance according to the following

table;

In the internal termination mode, the receiver termination of

each receiver is realized completely by internal resistors or by

the combination of internal and one fixed external resistor.

In the internal termination mode, the transmitter output should

be AC coupled to the transformer.

R/W

TERSEL0_n

Termination Impedance Select bit 0:

See description of bit D5 for the function of this bit.

R/W

RXTSEL

RX Termination

External

Internal

TXTSEL

TX Termination

External

Internal

TERSEL1 TERSEL0

Termination

100

Ω

110

Ω

120

Ω

XRT83SL34IV 数据表(PDF) 49 Page - Exar Corporation

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