数据搜索系统，热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

预览 PDF HTML

XRT83SL34IV 数据表(PDF) 58 Page - Exar Corporation

部件名 XRT83SL34IV
功能描述  QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
PDF  80 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  EXAR [Exar Corporation]
网页  http://www.exar.com
标志 EXAR - Exar Corporation

XRT83SL34IV 数据表(HTML) 58 Page - Exar Corporation

Back Button XRT83SL34IV Datasheet HTML 54Page - Exar Corporation XRT83SL34IV Datasheet HTML 55Page - Exar Corporation XRT83SL34IV Datasheet HTML 56Page - Exar Corporation XRT83SL34IV Datasheet HTML 57Page - Exar Corporation XRT83SL34IV Datasheet HTML 58Page - Exar Corporation XRT83SL34IV Datasheet HTML 59Page - Exar Corporation XRT83SL34IV Datasheet HTML 60Page - Exar Corporation XRT83SL34IV Datasheet HTML 61Page - Exar Corporation XRT83SL34IV Datasheet HTML 62Page - Exar Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 58 / 80 page
background image
XRT83SL34
QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. P1.0.8
PRELIMINARY
55
TABLE 25: MICROPROCESSOR REGISTER #6, BIT DESCRIPTION
REGISTER ADDRESS
0000110
0010110
0100110
0110110
CHANNEL_n
CHANNEL_0
CHANNEL_1
CHANNEL_2
CHANNEL_3
FUNCTION
REGISTER
TYPE
RESET
VALUE
BIT #NAME
D7
Reserved
RO
0
D6
DMOIS_n
Driver Monitor Output Interrupt Status: This bit is set to a
“1” every time the DMO status has changed since last read.
NOTE: This bit is reset upon read.
RUR
0
D5
FLSIS_n
FIFO Limit Interrupt Status: This bit is set to a “1” every time
when FIFO Limit (Read/Write pointer with +/- 3 bits apart) sta-
tus has changed since last read.
NOTE: This bit is reset upon read.
RUR
0
D4
LCVIS_n
Line Code Violation Interrupt Status: This bit is set to a “1”
every time when LCV status has changed since last read.
NOTE: This bit is reset upon read.
RUR
0
D3
NLCDIS_n
Network Loop-Code Detection Interrupt Status: This bit is
set to a “1” every time when NLCD status has changed since
last read.
NOTE: This bit is reset upon read.
RUR
0
D2
AISDIS_n
AIS Detection Interrupt Status: This bit is set to a “1” every
time when AISD status has changed since last read.
NOTE: This bit is reset upon read.
RUR
0
D1
RLOSIS_n
Receive Loss of Signal Interrupt Status: This bit is set to a
“1” every time RLOS status has changed since last read.
NOTE: This bit is reset upon read.
RUR
0
D0
QRPDIS_n
Quasi-Random Pattern Detection Interrupt Status: This bit
is set to a “1” every time when QRPD status has changed
since last read.
NOTE: This bit is reset upon read.
RUR
0



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com