XRT83SL34IV datasheet(55/80 Pages) EXAR

55 / 80 page

XRT83SL34

QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.0.8

TABLE 23: MICROPROCESSOR REGISTER #4, BIT DESCRIPTION

0000100

0010100

0100100

0110100

CHANNEL_n

CHANNEL_0

CHANNEL_1

CHANNEL_2

CHANNEL_3

FUNCTION

TYPE

RESET

VALUE

BIT #NAME

Reserved

DMOIE_n

DMO Interrupt Enable: Writing a “1” to this bit enables DMO

interrupt generation, writing a “0” masks it.

R/W

FLSIE_n

FIFO Limit Status Interrupt Enable: Writing a “1” to this bit

enables interrupt generation when the FIFO limit is within to 3

bits, writing a “0” to masks it.

R/W

LCVIE_n

Line Code Violation Interrupt Enable: Writing a “1” to this bit

enables Line Code Violation interrupt generation, writing a “0”

masks it.

R/W

NLCDIE_n

Network Loop-Code Detection Interrupt Enable: Writing a

“1” to this bit enables Network Loop-code detection interrupt

generation, writing a “0” masks it.

R/W

AISDIE_n

AIS Interrupt Enable: Writing a “1” to this bit enables Alarm

Indication Signal detection interrupt generation, writing a “0”

masks it.

R/W

RLOSIE_n

Receive Loss of Signal Interrupt Enable: Writing a “1” to this

bit enables Loss of Receive Signal interrupt generation, writing

a “0” masks it.

R/W

QRPDIE_n

QRSS Pattern Detection Interrupt Enable: Writing a “1” to

this bit enables QRSS pattern detection interrupt generation,

writing a “0” masks it.

R/W

XRT83SL34IV 数据表(PDF) 55 Page - Exar Corporation

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