XRT83SL34IV datasheet(56/80 Pages) EXAR

56 / 80 page

XRT83SL34

QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.0.8

PRELIMINARY

TABLE 24: MICROPROCESSOR REGISTER #5, BIT DESCRIPTION

0000101

0010101

0100101

0110101

CHANNEL_n

CHANNEL_0

CHANNEL_1

CHANNEL_2

CHANNEL_3

FUNCTION

TYPE

RESET

VALUE

BIT #NAME

Reserved

DMO_n

Driver Monitor Output: This bit is set to a “1” to indicate

transmit driver failure is detected. The value of this bit is based

on the current status of DMO for the corresponding channel. If

the DMOIE bit is enabled, any transition on this bit will gener-

ate an Interrupt.

FLS_n

FiFO Limit Status: This bit is set to a “1” to indicate that the jit-

ter attenuator read/write FIFO pointers are within +/- 3 bits. If

the FLSIE bit is enabled, any transition on this bit will generate

an Interrupt.

LCV_n

Line Code Violation: This bit is set to a “1” to indicate that the

receiver of channel n is currently detecting a Line Code Viola-

tion or an excessive number of zeros in the B8ZS or HDB3

modes. If the LCVIE bit is enabled, any transition on this bit will

generate an Interrupt.

XRT83SL34IV 数据表(PDF) 56 Page - Exar Corporation

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