XRT83SL34IV datasheet(29/80 Pages) EXAR

29 / 80 page

XRT83SL34

QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.0.8

TRANSMIT AND RECEIVE TERMINATIONS

The XRT83SL34 is a versatile LIU that can be programmed to use one Bill of Materials (BOM) for worldwide

applications for T1, J1 and E1. For specific applications the internal terminations can be disabled to allow the

use of existing components and/or designs.

RECEIVER (CHANNELS 0 - 3)

INTERNAL RECEIVE TERMINATION MODE

In Hardware mode, RXTSEL (Pin 83) can be tied “High” to select internal termination mode for all receive

channels or tied “Low” to select external termination mode. Individual channel control can only be done in Host

mode. By default the XRT83SL34 is set for external termination mode at power up or at Hardware reset.

In Host mode, bit 7 in the appropriate channel register, (Table 20, “Microprocessor Register #1, Bit

Description,” on page 46), is set “High” to select the internal termination mode for that specific receive channel.

1110

E1 Gain Mode

ITU G.703

Ω Coax

HDB3

1111

E1 Gain Mode

ITU G.703

120

Ω TP

HDB3

TABLE 6: RECEIVE TERMINATION CONTROL

RXTSEL

RX TERMINATION

EXTERNAL

INTERNAL

TABLE 5: RECEIVE EQUALIZER CONTROL AND TRANSMIT LINE BUILD-OUT SETTINGS

EQC4

EQC3

EQC2

EQC1

EQC0

E1/T1 MODE & RECEIVE

SENSITIVITY

TRANSMIT LBO

CABLE

CODING

XRT83SL34IV 数据表(PDF) 29 Page - Exar Corporation

XRT83SL34IV 数据表(HTML) 29 Page - Exar Corporation

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