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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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XRT83SL34IV 数据表(PDF) 76 Page - Exar Corporation |
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XRT83SL34IV 数据表(HTML) 76 Page - Exar Corporation |
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76 / 80 page  XRT83SL34 QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.0.8 PRELIMINARY 73 MICROPROCESSOR INTERFACE I/O TIMING INTEL INTERFACE TIMING - ASYNCHRONOUS The signals used for the Intel microprocessor interface are: Address Latch Enable (ALE), Read Enable (RD), Write Enable (WR), Chip Select (CS), Address and Data bits. The microprocessor interface uses minimum ex- ternal glue logic and is compatible with the timings of the 8051 or 80C188 with an 8-16 MHz clock frequency, and with the timings of x86 or i960 family or microprocessors. The interface timing shown in Figure 28 and Figure 30 is described in Table 49. FIGURE 27. RECEIVE CLOCK AND OUTPUT DATA TIMING FIGURE 28. INTEL ASYNCHRONOUS PROGRAMMED I/O INTERFACE TIMING RCLK R RCLK F RCLK RPOS or RNEG R DY R HO A DDR[6:0] DA T A [7 :0] RD_D S WR _R /W RD Y _ DT A C K V alid D ata for R ead ba ck D ata A v aila ble to W rite In to th e LIU READ O P ERAT IO N W RIT E O P E RAT IO N t 0 t 0 t 1 t 3 t 2 t 4 V a lid A ddres s V alid A d dre s s t 5 t 5 ALE_AS CS |
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