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STPMIC1 数据表(PDF) 111 Page - STMicroelectronics |
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STPMIC1 数据表(HTML) 111 Page - STMicroelectronics |
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111 / 140 page  6.5.13 Interrupt source register 3 ( INT_SRC_R3) Table 60. INT_SRC_R3 7 6 5 4 3 2 1 0 SWOUT_SH VBUSOTG_SH LDO6_OCP LDO5_OCP LDO4_OCP LDO3_OCP LDO2_OCP LDO1_OCP R R R R R R R R Address: 0xB2 Type: read register Default: 0x00 Description: interrupt source register 3. Register is default on RSTn assertion. State bit is 1 as long as event source is active. [7] SWOUT_SH: Current limitation detection on SWOUT 0: inactive 1: active [6] VBUSOTG_SH: Current limitation detection on VBUSOTG 0: inactive 1: active [5] LDO6_OCP: Current limitation detection on LDO6 0: inactive 1: active [4] LDO5_OCP: Current limitation detection on LDO5 0: inactive 1: active [3] LDO4_OCP: Current limitation detection on LDO4 0: inactive 1: active [2] LDO3_OCP: Current limitation detection on LDO3 0: inactive 1: active [1] LDO2_OCP: Current limitation detection on LDO2 0: inactive 1: active [0] LDO1_OCP: Current Limitation detection on LDO1 0: inactive 1: active STPMIC1 Interrupt registers DS12792 - Rev 7 page 111/140 |
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