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STPMIC1 数据表(PDF) 112 Page - STMicroelectronics |
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STPMIC1 数据表(HTML) 112 Page - STMicroelectronics |
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112 / 140 page ![]() 6.5.14 Interrupt source register 4 ( INT_SRC_R4) Table 61. INT_SRC_R4 7 6 5 4 3 2 1 0 SWIN reserved reserved reserved VINLOW reserved THW reserved R R R R R R R R Address: 0xB3 Type: read register Default: 0x00 Description: interrupt source register 4. Register is default on RSTn assertion. State bit is 1 as long as event source is active. [7] SWIN: SWIN event source state 0: inactive 1: active [6 :4] reserved [3] VINLOW: VINLOW event source state 0: inactive 1: active [2] reserved [1] THW: Temperature event source state 0: inactive 1: active [0] reserved STPMIC1 Interrupt registers DS12792 - Rev 7 page 112/140 |
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