SPC58EEX datasheet(148/154 Pages) STMICROELECTRONICS

148 / 154 page

Revision history

SPC58EEx, SPC58NEx

148/154

DS11646 Rev 4

03-April-2017

Table 43: Standby regulator specifications:

– Classification of parameter “IDDSBY” changed from “P” to “T”.

– Classification of parameter “IDDSBY” changed from “T” to “P”.

Table 17: Voltage monitor threshold definition:

Updated the figure.

Section 3.17: Flash memory:

Updated the section.

Table 50: Nexus debug port timing:

Classification of parameters “tEVTIPW” and “tEVTOPW” changed from “P” to “D”.

Table 56: DSPI CMOS master modified timing (full duplex and output only)

MTFE = 1, CPHA = 0 or 1:

Changed the Min value of tSCK (very strong) from 33 to 59.

Table 57: DSPI LVDS master timing — full duplex — modified transfer format

(MTFE = 1), CPHA = 0 or 1:

Added footnote “LVDS differential load considered is the capacitance on each

terminal of the differential pair...”.

Table 58: DSPI LVDS master timing – output only – timed serial bus mode

TSB = 1 or ITSB = 1, CPOL = 0 or 1, continuous SCK clock:

Added footnote “LVDS differential load considered is the capacitance on each

terminal of the differential pair...”.

Table 54: DSPI channel frequency support:

Added column to show slower and faster frequencies.

Section 5: Ordering information:

Renamed figure “Ordering information scheme” to “Commercial product

scheme”

Added tables: Table 82: Code Flash options, and Table 83: RAM options

Table 84. Document revision history (continued)

Date

Revision

Changes

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