AM2434...ALV datasheet(73/280 Pages) TI

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6.3.2 ADC

MAIN Domain Instances

Table 6-4. ADC0 Signal Descriptions

Signal Name [1] ((7))

Signal Type

[2]

Description [3]

ALV PIN [4]

ALX PIN [4]

ADC0_REFN (5) (6)

ADC0 Negative Voltage Reference. This is a negative

terminal analog input pin which must be treated like a high

transient power supply rail.

J16

ADC0_REFP (3) (4)

ADC0 Positive Voltage Reference. This is a positive

terminal analog input pin which must be treated like a high

transient power supply rail.

J15

ADC0_AIN0 (1) (2)

ADC Analog Input 0 / GPIO1_80 (Input Only)

G20

H21

ADC0_AIN1 (1) (2)

ADC Analog Input 1 / GPIO1_81 (Input Only)

F20

F19

ADC0_AIN2 (1) (2)

ADC Analog Input 2 / GPIO1_82 (Input Only)

E21

F21

ADC0_AIN3 (1) (2)

ADC Analog Input 3 / GPIO1_83 (Input Only)

D20

F20

ADC0_AIN4 (1) (2)

ADC Analog Input 4 / GPIO1_84 (Input Only)

G21

H20

ADC0_AIN5 (1) (2)

ADC Analog Input 5 / GPIO1_85 (Input Only)

F21

E21

ADC0_AIN6 (1) (2)

ADC Analog Input 6 / GPIO1_86 (Input Only)

F19

G20

ADC0_AIN7 (1) (2)

ADC Analog Input 7 / GPIO1_87 (Input Only)

E20

ADC_EXT_TRIGGER0

ADC Trigger Input

B16, C13

B7, B9

ADC_EXT_TRIGGER1

ADC Trigger Input

D14, D16

C11

(1)

This GPIO input signal has a debounce function. For more information on I/O Debounce configuration, see the TRM Device

Configuration chapter.

(2)

Only digital input signals are supported when configured as GPIO.

(3)

ADC0_REFP reference is a positive terminal analog input pin which must be treated like a high transient power supply rail.

ADC0_REFP must be connected to a power source capable of providing at least 4mA of current. ADC0_REFP may be connected

to the same power source as VDDA_ADC0 if the voltage tolerance of the supply provides an acceptable accuracy for the ADC

reference. If ADC0 is used, a high frequency decoupling capacitor must be connected on the back side of the PCB with vias between

the ADC0_REFP and ADC0_REFN pins. If ADC0 is not used, the decoupling capacitor is not required and ADC0_REFP may be

connected to VSS, if and only if VDDA_ADC0 has also been connected to VSS. See the Pin Connectivity Requirements section for

more information on ADC0 connectivity.

(4)

In PG1.0 J15 is assigned to VDDS_MMC0 (MMC0 PHY IO supply) and ADC0_REFP is internally connected to VDDA_ADC0. For

PG2.0 J15 is assigned to ADC0_REFP (ADC0 Positive Voltage Reference).

(5)

ADC0_REFP must be connected to a power source capable of providing at least 4mA of current. ADC0_REFP may be connected

to the same power source as VDDA_ADC0 if the voltage tolerance of the supply provides an acceptable accuracy for the ADC

reference. If ADC0 is used, a high frequency decoupling capacitor must be connected on the back side of the PCB with vias between

the ADC0_REFP and ADC0_REFN pins. If ADC0 is not used, the decoupling capacitor is not required and ADC0_REFP may be

connected to VSS, if and only if VDDA_ADC0 has also been connected to VSS. See the Pin Connectivity Requirements section for

more information on ADC0 connectivity.

(6)

In PG1.0 J16 is assigned to VSS (Ground) and ADC0_REFN is internally connected to VSS. For PG2.0 J16 is assigned to

ADC0_REFN (ADC0 Negative Voltage Reference).

(7)

The digital GPI functionality of these pins are controlled by the CTRLMMR_ADC0_CTRL[16] - GPI_MODE_EN register bit.

6.3.3 CPSW

MAIN Domain Instances

Table 6-5. CPSW3G0 RGMII1 Signal Descriptions

Signal Name [1]

Signal Type

[2]

Description [3]

ALV PIN [4]

ALX PIN [4]

RGMII1_RXC

RGMII Receive Clock

AA5, W13

U1, Y13

RGMII1_RX_CTL

RGMII Receive Control

V13, W6

U14, Y3

RGMII1_TXC

RGMII Transmit Clock

U14

W13

RGMII1_TX_CTL

RGMII Transmit Control

U15

W16

RGMII1_RD0

RGMII Receive Data 0

AA13, W5

AA11, T5

RGMII1_RD1

RGMII Receive Data 1

U12, Y5

R2, W11

RGMII1_RD2

RGMII Receive Data 2

V6, Y13

U2, Y15

RGMII1_RD3

RGMII Receive Data 3

V12, V5

AA13, T1

RGMII1_TD0

RGMII Transmit Data 0

V15

Y14

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AM2434, AM2432, AM2431

SPRSP65D – APRIL 2021 – REVISED AUGUST 2022

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