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AM2434...ALV 数据表(PDF) 89 Page - Texas Instruments

部件名 AM2434...ALV
功能描述  AM243x Sitara™ Microcontrollers
PDF  280 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

AM2434...ALV 数据表(HTML) 89 Page - Texas Instruments

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Table 6-44. GPMC0 Signal Descriptions (continued)
Signal Name [1] ((2))
Signal Type
[2]
Description [3]
ALV PIN [4]
ALX PIN [4]
GPMC0_AD17
IO
GPMC Data 17 Input/Output in A/D non-multiplexed mode
and additionally Address 18 Output in A/D multiplexed
mode
U8
W5
GPMC0_AD18
IO
GPMC Data 18 Input/Output in A/D non-multiplexed mode
and additionally Address 19 Output in A/D multiplexed
mode
W8
AA4
GPMC0_AD19
IO
GPMC Data 19 Input/Output in A/D non-multiplexed mode
and additionally Address 20 Output in A/D multiplexed
mode
V8
Y5
GPMC0_AD20
IO
GPMC Data 20 Input/Output in A/D non-multiplexed mode
and additionally Address 21 Output in A/D multiplexed
mode
Y8
AA5
GPMC0_AD21
IO
GPMC Data 21 Input/Output in A/D non-multiplexed mode
and additionally Address 22 Output in A/D multiplexed
mode
V13
U14
GPMC0_AD22
IO
GPMC Data 22 Input/Output in A/D non-multiplexed mode
and additionally Address 23 Output in A/D multiplexed
mode
AA7
Y2
GPMC0_AD23
IO
GPMC Data 23 Input/Output in A/D non-multiplexed mode
and additionally Address 24 Output in A/D multiplexed
mode
U13
V13
GPMC0_AD24
IO
GPMC Data 24 Input/Output in A/D non-multiplexed mode
and additionally Address 25 Output in A/D multiplexed
mode
W13
Y13
GPMC0_AD25
IO
GPMC Data 25 Input/Output in A/D non-multiplexed mode
and additionally Address 26 Output in A/D multiplexed
mode
U15
W16
GPMC0_AD26
IO
GPMC Data 26 Input/Output in A/D non-multiplexed mode
and additionally Address 27 Output in A/D multiplexed
mode
U14
W13
GPMC0_AD27
IO
GPMC Data 27 Input/Output in A/D non-multiplexed mode
and additionally Address 28 Output in A/D multiplexed
mode
AA8
V5
GPMC0_AD28
IO
GPMC Data 28 Input/Output in A/D non-multiplexed mode
and additionally Address 29 Output in A/D multiplexed
mode
U9
W2
GPMC0_AD29
IO
GPMC Data 29 Input/Output in A/D non-multiplexed mode
and additionally Address 30 Output in A/D multiplexed
mode
W9
V6
GPMC0_AD30
IO
GPMC Data 30 Input/Output in A/D non-multiplexed mode
and additionally Address 31 Output in A/D multiplexed
mode
AA9
AA7
GPMC0_AD31
IO
GPMC Data 31 Input/Output in A/D non-multiplexed mode
and additionally Address 0 Output in A/D multiplexed mode
Y9
Y7
GPMC0_BE0n_CLE
O
GPMC Lower-Byte Enable (active low) or Command Latch
Enable
P17
GPMC0_BE1n
O
GPMC Upper-Byte Enable (active low)
T19
P21
GPMC0_BE2n
O
GPMC Upper-Byte Enable (active low)
V9
W6
GPMC0_BE3n
O
GPMC Upper-Byte Enable (active low)
AA14
AA14
GPMC0_CSn0
O
GPMC Chip Select 0 (active low)
R19
GPMC0_CSn1
O
GPMC Chip Select 1 (active low)
R20
GPMC0_CSn2
O
GPMC Chip Select 2 (active low)
P19
GPMC0_CSn3
O
GPMC Chip Select 3 (active low)
R21
GPMC0_WAIT0
I
GPMC External Indication of Wait
W19
GPMC0_WAIT1
I
GPMC External Indication of Wait
Y18
(1)
The RXACTIVE bit of the CTRLMMR_PADCONFIG32 register must be set to 0x1 and the TX_DIS bit of the
CTRLMMR_PADCONFIG32 register must be reset to 0x0 when GPMC0 is operating in synchronous mode.
(2)
The GPMC0 interface is not supported by the AM243x_ALX device package. See AM243x_ALX Package - Unsupported Interfaces
and Signals for additional details.
www.ti.com
AM2434, AM2432, AM2431
SPRSP65D – APRIL 2021 – REVISED AUGUST 2022
Copyright © 2022 Texas Instruments Incorporated
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