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AM2434...ALV 数据表(PDF) 100 Page - Texas Instruments |
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AM2434...ALV 数据表(HTML) 100 Page - Texas Instruments |
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100 / 280 page  Table 6-65. PRU_ICSSG0 Signal Descriptions (continued) Signal Name [1] Signal Type [2] Description [3] ALV PIN [4] ALX PIN [4] PRG0_RGMII2_RX_CTL I PRU_ICSSG0 RGMII Receive Control W3 L3 PRG0_RGMII2_TXC IO PRU_ICSSG0 RGMII Transmit Clock AA4 T3 PRG0_RGMII2_TX_CTL O PRU_ICSSG0 RGMII Transmit Control U5 M4 PRG0_RGMII1_RD0 I PRU_ICSSG0 RGMII Receive Data Y1 J3 PRG0_RGMII1_RD1 I PRU_ICSSG0 RGMII Receive Data R4 J4 PRG0_RGMII1_RD2 I PRU_ICSSG0 RGMII Receive Data U2 G1 PRG0_RGMII1_RD3 I PRU_ICSSG0 RGMII Receive Data V2 H1 PRG0_RGMII1_TD0 O PRU_ICSSG0 RGMII Transmit Data Y3 L1 PRG0_RGMII1_TD1 O PRU_ICSSG0 RGMII Transmit Data AA3 K1 PRG0_RGMII1_TD2 O PRU_ICSSG0 RGMII Transmit Data R6 N1 PRG0_RGMII1_TD3 O PRU_ICSSG0 RGMII Transmit Data V4 N2 PRG0_RGMII2_RD0 I PRU_ICSSG0 RGMII Receive Data Y2 L5 PRG0_RGMII2_RD1 I PRU_ICSSG0 RGMII Receive Data W2 J2 PRG0_RGMII2_RD2 I PRU_ICSSG0 RGMII Receive Data V3 M2 PRG0_RGMII2_RD3 I PRU_ICSSG0 RGMII Receive Data T4 L2 PRG0_RGMII2_TD0 O PRU_ICSSG0 RGMII Transmit Data W4 P1 PRG0_RGMII2_TD1 O PRU_ICSSG0 RGMII Transmit Data Y4 P2 PRG0_RGMII2_TD2 O PRU_ICSSG0 RGMII Transmit Data T6 T4 PRG0_RGMII2_TD3 O PRU_ICSSG0 RGMII Transmit Data U6 R5 PRG0_UART0_CTSn I PRU_ICSSG0 UART Clear to Send (active low) W6 Y3 PRG0_UART0_RTSn O PRU_ICSSG0 UART Request to Send (active low) AA5 U1 PRG0_UART0_RXD I PRU_ICSSG0 UART Receive Data Y5 R2 PRG0_UART0_TXD O PRU_ICSSG0 UART Transmit Data V6 U2 Table 6-66. PRU_ICSSG1 Signal Descriptions Signal Name [1] Signal Type [2] Description [3] ALV PIN [4] ALX PIN [4] PRG1_ECAP0_IN_APWM_OUT IO PRU_ICSSG1 Enhanced Capture (ECAP) Input or Auxiliary PWM (APWM) output V12 AA13 PRG1_ECAP0_SYNC_IN I PRU_ICSSG1 ECAP Sync Input Y13 Y15 PRG1_ECAP0_SYNC_OUT O PRU_ICSSG1 ECAP Sync Output AA14 AA14 PRG1_IEP0_EDIO_OUTVALID (1) O PRU_ICSSG1 Industrial Ethernet Digital I/O Outvalid D14 PRG1_IEP0_EDC_LATCH_IN0 I PRU_ICSSG1 Industrial Ethernet Distributed Clock Latch Input V7 Y4 PRG1_IEP0_EDC_LATCH_IN1 I PRU_ICSSG1 Industrial Ethernet Distributed Clock Latch Input U13 V13 PRG1_IEP0_EDC_SYNC_OUT0 O PRU_ICSSG1 Industrial Ethernet Distributed Clock Sync Output W7 U3 PRG1_IEP0_EDC_SYNC_OUT1 O PRU_ICSSG1 Industrial Ethernet Distributed Clock Sync Output U7 T2 PRG1_IEP0_EDIO_DATA_IN_OUT2 8 IO PRU_ICSSG1 Industrial Ethernet Digital I/O Data Input/ Output U15 W16 PRG1_IEP0_EDIO_DATA_IN_OUT2 9 IO PRU_ICSSG1 Industrial Ethernet Digital I/O Data Input/ Output U14 W13 PRG1_IEP0_EDIO_DATA_IN_OUT3 0 IO PRU_ICSSG1 Industrial Ethernet Digital I/O Data Input/ Output V14 Y16 PRG1_IEP0_EDIO_DATA_IN_OUT3 1 IO PRU_ICSSG1 Industrial Ethernet Digital I/O Data Input/ Output W14 U13 PRG1_IEP1_EDC_LATCH_IN0 I PRU_ICSSG1 Industrial Ethernet Distributed Clock Latch Input Y13 Y15 PRG1_IEP1_EDC_LATCH_IN1 I PRU_ICSSG1 Industrial Ethernet Distributed Clock Latch Input V15 Y14 AM2434, AM2432, AM2431 SPRSP65D – APRIL 2021 – REVISED AUGUST 2022 www.ti.com 100 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AM2434 AM2432 AM2431 |
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