 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
AM2434...ALV 数据表(PDF) 76 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
AM2434...ALV 数据表(HTML) 76 Page - Texas Instruments |
|
|
76 / 280 page  6.3.4 CPTS MAIN Domain Instances Table 6-12. CP GEMAC CPTS0 Signal Descriptions Signal Name [1] Signal Type [2] Description [3] ALV PIN [4] ALX PIN [4] CP_GEMAC_CPTS0_RFT_CLK (1) I CPTS Reference Clock Input to CPSW3G0 CPTS D18 CP_GEMAC_CPTS0_TS_COMP O CPTS Time Stamp Counter Compare Output from CPSW3G0 CPTS E15, K18, W1 B12, G2, K18 CP_GEMAC_CPTS0_TS_SYNC O CPTS Time Stamp Counter Bit Output from CPSW3G0 CPTS B16, D16, K19, U1 B9, C11, E1, K20 CP_GEMAC_CPTS0_HW1TSPUSH I CPTS Hardware Time Stamp Push Input to CPSW3G0 CPTS E14, L21, V1 A12, J19, K4 CP_GEMAC_CPTS0_HW2TSPUSH I CPTS Hardware Time Stamp Push Input to CPSW3G0 CPTS E16, K21, T1 A11, E2, J18 (1) The CP_GEMAC_CPTS0_RFT_CLK signal is not supported by the AM243x_ALX device package. See AM243x_ALX Package - Unsupported Interfaces and Signals for additional details. Table 6-13. CPTS0 Signal Descriptions Signal Name [1] Signal Type [2] Description [3] ALV PIN [4] ALX PIN [4] CPTS0_RFT_CLK (2) I CPTS Reference Clock Input D18 CPTS0_TS_COMP O CPTS Time Stamp Counter Compare Output C13, W1, W7 B7, G2, U3 CPTS0_TS_SYNC O CPTS Time Stamp Counter Bit Output D14, U1, U7 E1, T2 CPTS0_HW1TSPUSH I CPTS Hardware Time Stamp Push Input to Time Sync Router C18, V1, V7 A17, K4, Y4 CPTS0_HW2TSPUSH I CPTS Hardware Time Stamp Push Input to Time Sync Router B19, T1, U13 B18, E2, V13 SYNC0_OUT (1) O CPTS Time Stamp Generator Bit 0 Output from Time Sync Router D18 SYNC1_OUT O CPTS Time Stamp Generator Bit 1 Output from Time Sync Router A19 A18 SYNC2_OUT O CPTS Time Stamp Generator Bit 2 Output from Time Sync Router A17 B13 SYNC3_OUT O CPTS Time Stamp Generator Bit 3 Output from Time Sync Router B17 A14 (1) The SYNC0_OUT signal is not supported by the AM243x_ALX device package. See AM243x_ALX Package - Unsupported Interfaces and Signals for additional details. (2) The CPTS0_RFT_CLK signal is not supported by the AM243x_ALX device package. See AM243x_ALX Package - Unsupported Interfaces and Signals for additional details. 6.3.5 DDRSS MAIN Domain Instances Table 6-14. DDRSS0 Signal Descriptions Signal Name [1] ((2)) Signal Type [2] Description [3] ALV PIN [4] ALX PIN [4] DDR0_ACT_n O DDRSS Activation Command H2 DDR0_ALERT_n IO DDRSS Alert H1 DDR0_CAS_n O DDRSS Column Address Strobe J5 DDR0_PAR O DDRSS Command and Address Parity K5 DDR0_RAS_n O DDRSS Row Address Strobe F6 DDR0_WE_n O DDRSS Write Enable H4 DDR0_A0 O DDRSS Address Bus D2 DDR0_A1 O DDRSS Address Bus C5 DDR0_A2 O DDRSS Address Bus E2 DDR0_A3 O DDRSS Address Bus D4 DDR0_A4 O DDRSS Address Bus D3 AM2434, AM2432, AM2431 SPRSP65D – APRIL 2021 – REVISED AUGUST 2022 www.ti.com 76 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AM2434 AM2432 AM2431 |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
