AM2434...ALV datasheet(87/280 Pages) TI

87 / 280 page

Table 6-43. MCU_GPIO0 Signal Descriptions (continued)

Signal Name [1]

Signal Type

[2]

Description [3]

ALV PIN [4]

ALX PIN [4]

MCU_GPIO0_15

General Purpose Input/Output

MCU_GPIO0_16 (1) (2)

General Purpose Input/Output

MCU_GPIO0_17 (1) (2)

General Purpose Input/Output

MCU_GPIO0_18 (3)

IOD

General Purpose Input/Output

MCU_GPIO0_19 (4)

IOD

General Purpose Input/Output

A10

MCU_GPIO0_20 (1) (2)

General Purpose Input/Output

A11

MCU_GPIO0_21 (1) (2)

General Purpose Input/Output

B10

MCU_GPIO0_22

General Purpose Input/Output

B13

(1)

This MCU_GPIO0 signal is not supported by the AM243x_ALX device package. See AM243x_ALX Package - Unsupported

Interfaces and Signals for additional details.

(2)

This GPIO input signal has a debounce function. For more information on I/O Debounce configuration, see the TRM Device

Configuration chapter.

(3)

MCU_GPIO0_18 is implemented with the I2C OD FS (Open Drain Fail Safe) voltage buffer.

(4)

MCU_GPIO0_19 is implemented with the I2C OD FS (Open Drain Fail Safe) voltage buffer.

6.3.12 GPMC

MAIN Domain Instances

Table 6-44. GPMC0 Signal Descriptions

Signal Name [1] ((2))

Signal Type

[2]

Description [3]

ALV PIN [4]

ALX PIN [4]

GPMC0_ADVn_ALE

GPMC Address Valid (active low) or Address Latch Enable

P16

GPMC0_CLK (1)

GPMC Clock

R17

GPMC0_DIR

GPMC Data Bus Signal Direction Control

N17

GPMC0_OEn_REn

GPMC Output Enable (active low) or Read Enable (active

low)

R18

GPMC0_WEn

GPMC Write Enable (active low)

T21

GPMC0_WPn

GPMC Flash Write Protect (active low)

N16

GPMC0_A0

GPMC Address 0 Output. Only used to effectively address

8-bit data non-multiplexed memories

U2, U7

G1, T2

GPMC0_A1

GPMC address 1 Output in A/D non-multiplexed mode and

Address 17 in A/D multiplexed mode

AA2, V7

K2, Y4

GPMC0_A2

GPMC address 2 Output in A/D non-multiplexed mode and

Address 18 in A/D multiplexed mode

T2, W7

H5, U3

GPMC0_A3

GPMC address 3 Output in A/D non-multiplexed mode and

Address 19 in A/D multiplexed mode

V4, W11

AA10, N2

GPMC0_A4

GPMC address 4 Output in A/D non-multiplexed mode and

Address 20 in A/D multiplexed mode

U4, V11

N3, Y10

GPMC0_A5

GPMC address 5 Output in A/D non-multiplexed mode and

Address 21 in A/D multiplexed mode

AA12, V1

K4, Y11

GPMC0_A6

GPMC address 6 Output in A/D non-multiplexed mode and

Address 22 in A/D multiplexed mode

W1, Y12

G2, V12

GPMC0_A7

GPMC address 7 Output in A/D non-multiplexed mode and

Address 23 in A/D multiplexed mode

W12, Y4

P2, Y12

GPMC0_A8

GPMC address 8 Output in A/D non-multiplexed mode and

Address 24 in A/D multiplexed mode

AA13, T6

AA11, T4

GPMC0_A9

GPMC address 9 Output in A/D non-multiplexed mode and

Address 25 in A/D multiplexed mode

U11, U6

R5, V10

GPMC0_A10

GPMC address 10 Output in A/D non-multiplexed mode

and Address 26 in A/D multiplexed mode

U5, V15

M4, Y14

GPMC0_A11

GPMC address 11 Output in A/D non-multiplexed mode

and unused in A/D multiplexed mode

AA4, U12

T3, W11

GPMC0_A12

GPMC address 12 Output in A/D non-multiplexed mode

and unused in A/D multiplexed mode

P2, V14

E4, Y16

GPMC0_A13

GPMC address 13 Output in A/D non-multiplexed mode

and unused in A/D multiplexed mode

P3, W14

D2, U13

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SPRSP65D – APRIL 2021 – REVISED AUGUST 2022

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