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AM2434...ALV 数据表(PDF) 15 Page - Texas Instruments

部件名 AM2434...ALV
功能描述  AM243x Sitara™ Microcontrollers
PDF  280 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

AM2434...ALV 数据表(HTML) 15 Page - Texas Instruments

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6 Terminal Configuration and Functions
6.1 Pin Diagram
Note
The terms "ball", "pin", and "terminal" are used interchangeably throughout the document. An attempt
is made to use "ball" only when referring to the physical package.
The diagrams in this section are used in conjunction with the other Terminal Configuration and Functions tables
to locate signal names and ball grid numbers.
6.1.1 AM243x ALV Pin Diagram
ALV FCBGA-N441 Pin Diagram shows the ball locations for the lidded 441-ball flip chip ball grid array (FCBGA)
package.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
Not to scale
VSS
PRG0_PRU0
_GPO4
PRG0_PRU0
_GPO12
PRG0_PRU1
_GPO16
PRG0_PRU0
_GPO10
PRG1
_MDIO0
_MDIO
PRG1_PRU0
_GPO6
PRG1_PRU0
_GPO11
PRG1_PRU0
_GPO14
PRG1_PRU1
_GPO11
PRG1_PRU1
_GPO14
PRG1_PRU1
_GPO2
PRG1_PRU1
_GPO5
PRG1_PRU1
_GPO17
VSS
SERDES0
_TX0_N
SERDES0
_TX0_P
VSS
USB0_DP
USB0_DM
VSS
PRG0_PRU0
_GPO0
PRG0_PRU1
_GPO0
PRG0_PRU0
_GPO11
PRG0_PRU1
_GPO12
PRG0_PRU1
_GPO9
PRG1
_MDIO0
_MDC
PRG1_PRU0
_GPO0
PRG1_PRU0
_GPO4
PRG1_PRU0
_GPO15
PRG1_PRU1
_GPO16
PRG1_PRU1
_GPO15
PRG1_PRU1
_GPO3
PRG1_PRU1
_GPO18
VSS
SERDES0
_RX0_N
SERDES0
_RX0_P
VSS
GPMC0
_WAIT1
VSS
GPMC0
_AD15
GPMC0
_AD14
PRG0_PRU0
_GPO19
PRG0_PRU1
_GPO1
PRG0_PRU1
_GPO4
PRG0_PRU1
_GPO11
PRG0_PRU1
_GPO7
PRG0_PRU0
_GPO9
PRG1_PRU0
_GPO19
PRG1_PRU0
_GPO2
PRG1_PRU0
_GPO13
VSS
PRG1_PRU1
_GPO0
PRG1_PRU1
_GPO4
PRG1_PRU0
_GPO8
PRG1_PRU1
_GPO10
RSVD4
SERDES0
_REFCLK0N
SERDES0
_REFCLK0P
VSS
GPMC0
_WAIT0
GPMC0
_AD11
GPMC0
_AD12
PRG0_PRU0
_GPO18
PRG0_PRU0
_GPO3
PRG0_PRU1
_GPO2
PRG0_PRU0
_GPO14
PRG0_PRU1
_GPO17
PRG0_PRU1
_GPO10
PRG1_PRU0
_GPO18
PRG1_PRU0
_GPO3
PRG1_PRU0
_GPO16
PRG1_PRU1
_GPO12
PRG1_PRU1
_GPO1
PRG1_PRU1
_GPO19
PRG1_PRU0
_GPO5
PRG1_PRU1
_GPO9
PRG1_PRU1
_GPO7
RSVD5
VSS
GPMC0
_AD13
GPMC0_AD8
GPMC0_AD6
GPMC0_AD7
PRG0_PRU0
_GPO17
PRG0_PRU0
_GPO2
VSS
PRG0_PRU0
_GPO16
PRG0_PRU1
_GPO15
PRG0_PRU1
_GPO14
PRG1_PRU0
_GPO17
PRG1_PRU0
_GPO1
PRG1_PRU0
_GPO12
PRG1_PRU1
_GPO13
PRG1_PRU1
_GPO6
PRG1_PRU1
_GPO8
PRG1_PRU0
_GPO7
PRG1_PRU0
_GPO10
PRG1_PRU0
_GPO9
USB0_ID
USB0
_RCALIB
GPMC0_AD4
GPMC0_AD5
GPMC0_AD3
GPMC0_AD1
PRG0_PRU0
_GPO7
PRG0_PRU0
_GPO8
PRG0_PRU0
_GPO6
PRG0_PRU1
_GPO3
PRG0_PRU0
_GPO15
PRG0_PRU1
_GPO13
CAP_VDDS1
VSS
VDDSHV2
VSS
VSS
VDDA_0P85
_USB0
SERDES0
_REXT
USB0_VBUS
VSS
VSS
GPMC0_AD9
GPMC0_AD2
GPMC0
_BE1n
GPMC0_AD0
GPMC0_WEn
PRG0_PRU1
_GPO8
PRG0_PRU1
_GPO19
PRG0_PRU0
_GPO5
PRG0_PRU0
_GPO1
PRG0_PRU1
_GPO6
PRG0_PRU0
_GPO13
VSS
VDDSHV2
VSS
VDDSHV2
CAP_VDDS2
VSS
VDDA_3P3
_USB0
VDDA_1P8
_SERDES0
VDDA_1P8
_USB0
GPMC0
_AD10
GPMC0_CLK
GPMC0_OEn
_REn
GPMC0
_CSn0
GPMC0
_CSn1
GPMC0
_CSn3
VSS
PRG0
_MDIO0
_MDIO
PRG0
_MDIO0
_MDC
PRG0_PRU1
_GPO5
PRG0_PRU1
_GPO18
VSS
VDDSHV1
VSS
VDD_CORE
VSS
VDDA_0P85
_SERDES0
_C
VDDA_0P85
_SERDES0
VDDA_0P85
_SERDES0
VDDSHV3
VDDSHV3
GPMC0
_ADVn_ALE
GPMC0
_BE0n_CLE
VSS
GPMC0
_CSn2
OSPI0_D5
OSPI0_D4
DDR0_DQS1
DDR0_DQ15
DDR0_DQ13
DDR0_DQ12
DDR0_DQ8
VDDSHV1
VSS
VDD_CORE
VSS
VDD_CORE
VSS
VDDA_PLL0
VSS
CAP_VDDS3
VSS
GPMC0_WPn
GPMC0_DIR
OSPI0_D6
OSPI0_DQS
OSPI0_CLK
OSPI0
_LBCLKO
DDR0_DQS1
_n
DDR0_DM1
DDR0_DQ11
DDR0_DQ14
DDR0_A12
VSS
VDDSHV1
VSS
VDD_CORE
VSS
VDD_CORE
VSS
VDDR_CORE
VDDSHV4
VDDSHV4
CAP_VDDS4
OSPI0_D7
OSPI0_D1
OSPI0_D0
OSPI0_D2
OSPI0_D3
VSS
DDR0_DQ10
VSS
DDR0_DQ9
DDR0_A7
VDDS_DDR
VSS
VDD_CORE
VSS
VDDR_CORE
VDDA
_TEMP1
VDD_CORE
CAP_VDDS5
VDDSHV5
VDDSHV5
VSS
OSPI0
_CSn3
OSPI0
_CSn1
OSPI0
_CSn0
MMC1_CLK
MMC1_DAT1
RSVD7
RSVD6
DDR0_A10
DDR0_A13
DDR0_PAR
VSS
VDDS_DDR
VSS
VDD_CORE
VMON_VSYS
VDD_CORE
VDDA_MCU
VDD_MMC0
VDDS_MMC0
CAP
_VDDSHV
_MMC1
VMON_1P8
_MCU
OSPI0
_CSn2
MMC1_DAT3
MMC1_DAT2
MMC0_DAT0
MMC1_DAT0
DDR0_A11
DDR0_A6
DDR0_A8
DDR0_A9
DDR0_CAS
_n
VDDS_DDR
VSS
VDDS_DDR
_C
VSS
VDD_CORE
VDDA_PLL2
VDD_CORE
VDDA_ADC
VSS
ADC0_REFP
ADC0_REFN
MMC0_DAT3
MMC0_DAT2
MMC1_CMD
MMC0_DAT1
MMC0_CMD
DDR0
_ALERT_n
DDR0_ACT
_n
DDR0_BG1
DDR0_WE_n
DDR0_CAL0
VSS
VDDS_DDR
VSS
VDDA_PLL1
CAP_VDDS
_MCU
VSS
CAP_VDDS0
VDDS_OSC
VDD_DLL
_MMC0
VDDA_3P3
_SDIO
RSVD0
MMC0_DAT4
MMC0_DAT6
MMC0_DAT5
VSS
VSS
VSS
DDR0_BG0
VSS
DDR0_BA0
DDR0_BA1
VDDS_DDR
VSS
VDDSHV
_MCU
VSS
VDDSHV
_MCU
VDDA
_TEMP0
VDDSHV0
RSVD2
VDDSHV0
VPP
VSS
MMC0_DAT7
MMC0_CLK
MMC0_DS
ADC0_AIN0
ADC0_AIN4
DDR0_CK0
DDR0_A5
DDR0_CKE1
DDR0_CKE0
DDR0_ODT1
DDR0_RAS
_n
VDDS_DDR
VSS
VDDSHV
_MCU
VSS
VDDSHV0
RSVD8
VMON_3P3
_MCU
VMON_3P3
_SOC
VSS
RESETSTA
Tz
RSVD3
MMC0
_CALPAD
ADC0_AIN6
ADC0_AIN1
ADC0_AIN5
DDR0_CK0
_n
DDR0_A2
DDR0_CS0
_n
DDR0_CS1
_n
DDR0_ODT0
MCU_SPI0
_CLK
MCU_SPI0
_D0
MCU_UART0
_RTSn
MCU_I2C0
_SCL
EMU1
VSS
VMON_1P8
_SOC
VSS
UART1_TXD
UART1_RXD
UART1
_RTSn
PORz_OUT
RESET
_REQz
USB0
_DRVVBUS
ADC0_AIN7
ADC0_AIN2
VSS
DDR0_A0
DDR0_A4
DDR0_A3
DDR0
_RESET0_n
MCU_SPI0
_CS0
MCU_SPI1
_CLK
MCU_UART0
_CTSn
MCU_UART1
_TXD
EMU0
TRSTn
SPI0_CS0
SPI0_CLK
SPI1_CS1
UART0_RXD
UART1
_CTSn
MCAN1_RX
ECAP0_IN
_APWM_OUT
MMC1_SDCD
ADC0_AIN3
RSVD1
DDR0_DQS0
DDR0_DQ6
VSS
DDR0_DQ5
DDR0_A1
MCU_SPI0
_CS1
MCU_SPI1
_D0
MCU_SPI1
_D1
MCU_UART1
_RXD
VSS
TDI
TMS
SPI0_CS1
SPI1_CLK
VSS
UART0_TXD
MCAN1_TX
I2C1_SCL
EXTINTn
MMC1_SDWP
MCU_OSC0
_XI
DDR0_DQS0
_n
DDR0_DM0
DDR0_DQ4
DDR0_DQ7
DDR0_DQ2
MCU_SPI0
_D1
MCU_SPI1
_CS1
MCU_UART1
_CTSn
MCU_UART1
_RTSn
MCU_I2C1
_SDA
TCK
MCU
_RESETz
MCU_RESETS
TATz
SPI1_CS0
SPI1_D0
UART0
_CTSn
MCAN0_RX
I2C0_SDA
I2C1_SDA
MCU_OSC0
_XO
MCU_PORz
VSS
DDR0_DQ1
DDR0_DQ0
DDR0_DQ3
VSS
VSS
MCU_SPI1
_CS0
MCU_UART0
_TXD
MCU_UART0
_RXD
MCU_I2C0
_SDA
MCU_I2C1
_SCL
TDO
SPI0_D0
SPI0_D1
SPI1_D1
UART0
_RTSn
MCAN0_TX
I2C0_SCL
EXT
_REFCLK1
MCU
_SAFETY
_ERRORn
VSS
Figure 6-1. ALV FCBGA-N441 Pin Diagram (Bottom View)
www.ti.com
AM2434, AM2432, AM2431
SPRSP65D – APRIL 2021 – REVISED AUGUST 2022
Copyright © 2022 Texas Instruments Incorporated
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