AM2434...ALV datasheet(2/280 Pages) TI

2 / 280 page

Security:

• Secure Boot supported

– Hardware-enforced Root-of-Trust (RoT)

– Support to switch RoT via backup key

– Support for takeover protection, IP protection,

and anti-roll back protection

• Support for cryptographic acceleration

– Session-aware cryptographic engine with ability

to auto-switch key-material based on incoming

data stream

– DMA support

– Supports cryptographic cores

• AES – 128/192/256-bit key sizes

• 3DES – 56/112/168-bit key sizes

• MD5, SHA1

• SHA2 – 224/256/384/512-bit key sizes

• DRBG with true random number generator

• PKA (Public Key Accelerator) to Assist in

RSA/ECC processing

• Debugging security

– Secure software-controlled debug access

– Security aware debugging

• Secure storage support

• On-the-Fly encryption (OTFE) support for OSPI in

XIP mode

• Networking security support for data (Payload)

encryption/authentication via packet-based

hardware cryptographic engine

• DMSC-L co-processor for security and key

management, with dedicated device level

interconnect

General connectivity peripherals:

• 6× Inter-Integrated Circuit (I2C) ports

• 9× configurable Universal Asynchronous Receive/

Transmit (UART) modules

• 1× 12-bit Analog-to-Digital Converters (ADC)

– Configurable sample rate up to 4 MSPS

– 8× multiplexed analog inputs

• 7× Multichannel Serial Peripheral Interfaces (SPI)

controllers

• 3× General-Purpose I/O (GPIO) modules

Industrial and control interfaces:

• 9× Enhanced Pulse-Width Modulator (EPWM)

modules

• 3× Enhanced Capture (ECAP) modules

• 3× Enhanced Quadrature Encoder Pulse (EQEP)

modules

• 2× Modular Controller Area Network (MCAN)

modules with full CAN-FD support

• 2× Fast Serial Interface Transmitter (FSITX) cores

• 6× Fast Serial Interface Receiver (FSIRX) cores

High-speed interfaces:

• 1× Integrated Ethernet switch supporting up to 2

external ports (CPSW3G)

– Up to 2 Ethernet ports

• RGMII (10/100/1000)

• RMII (10/100)

– IEEE 1588 (2008 Annex D, Annex E, Annex F)

with 802.1AS PTP

– Clause 45 MDIO PHY management

– Energy efficient Ethernet (802.3az)

• 1× PCI-Express® Gen2 controller (PCIE)

– Supports Gen2 Single Lane operation

• 1× USB 3.1 Dual-Role Device (DRD) Subsystem

(USBSS)

– Port configurable as USB host, USB device, or

USB Dual-Role device

– USB device: High-speed (480 Mbps) and Full-

speed (12 Mbps)

– USB host: SuperSpeed Gen 1 (5 Gbps), High-

speed (480 Mbps),Full-speed (12 Mbps), and

Low-speed (1.5 Mbps)

– Integrated USB VBUS detection

• 1× Serializer/Deserializer (SERDES)

– One SerDes PHY lane to support either PCI-

Express® Gen2 or USB Super-Speed Gen1

Media and data storage:

• 2× MultiMedia Card/Secure Digital (MMCSD)

interfaces

– One 8-bit for eMMC (MMCSD0)

– One 4-bit for SD/SDIO (MMCSD1)

– Integrated analog switch for voltage switching

between 3.3V to 1.8V for high-speed cards

• 1× General-Purpose Memory Controller (GPMC)

– 16-bit parallel bus with 133 MHz clock or

– 32-bit parallel bus with 100 MHz clock

– Error Location Module (ELM) support

• 1× Flash Subsystem (FSS) that can be configured

as one Octal SPI (OSPI) or one Quad SPI (QSPI)

flash interface

Power management:

• Simplified power sequencing requirements

• Dual-voltage I/O Support

• Integrated SDIO LDO for handling automatic

voltage transition for SD interface

• Integrated voltage supervisor for safety monitoring

of over-under voltage conditions

• Integrated power supply glitch detector for

detecting fast supply transients

AM2434, AM2432, AM2431

SPRSP65D – APRIL 2021 – REVISED AUGUST 2022

www.ti.com

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