AM2434...ALV datasheet(191/280 Pages) TI

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7.10.5.11.1 MCSPI — Controller Mode

Table 7-62, Figure 7-54, Table 7-63, and Figure 7-55 present timing requirements and switching characteristics

for SPI – Controller Mode.

Table 7-62. MCSPI Timing Requirements – Controller Mode

see Figure 7-54

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

SM4

tsu(POCI-SPICLK)

Setup time, SPIn_D[x] valid before SPIn_CLK active edge

2.8

SM5

th(SPICLK-POCI)

Hold time, SPIn_D[x] valid after SPIn_CLK active edge

SPI_CS[i] (OUT)

SPI_SCLK (OUT)

SPI_D[x] (IN)

SPI_CS[i] (OUT)

SPI_SCLK (OUT)

SPI_D[x] (IN)

Bit n-1

Bit n-2

Bit n-3

Bit n-4

Bit 0

Bit n-1

Bit n-2

Bit n-3

Bit 1

Bit 0

PHA=0

EPOL=1

PHA=1

EPOL=1

POL=0

POL=1

POL=0

POL=1

SM8

SM9

SM3

SM1

SM2

SM1

SM8

SM9

SM3

SM1

SM2

SM1

SM2

SM3

SM2

SM3

SM4

SM5

SM4

SM5

SM4

SM5

SPRSP08_TIMING_McSPI_02

Figure 7-54. MCSPI Controller Mode Receive Timing

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AM2434, AM2432, AM2431

SPRSP65D – APRIL 2021 – REVISED AUGUST 2022

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