STM32F405 datasheet(59/204 Pages) STMICROELECTRONICS

59 / 204 page

DS8626 Rev 9

59/203

STM32F405xx, STM32F407xx

Pinouts and pin description

143 C6 171

PDR_ON

64 A1

144 C5 172

VDD

S-

D4 173

PI4

I/O

TIM8_BKIN / DCMI_D5/

EVENTOUT

C4 174

PI5

I/O

TIM8_CH1 /

DCMI_VSYNC/

EVENTOUT

C3 175

PI6

I/O

TIM8_CH2 / DCMI_D6/

EVENTOUT

C2 176

PI7

I/O

TIM8_CH3 / DCMI_D7/

EVENTOUT

1. UFBGA176 F6, F7, F8, F9, F10, G6, G7, G8, G9, G10, H6, H7, H8, H9, H10, J6, J7, J8, J9, J10, K6, K7, K8, K9 and K10 balls

are connected to VSS for heat dissipation and package mechanical stability.

2. Function availability depends on the chosen device.

3. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current

(3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited:

- The speed should not exceed 2 MHz with a maximum load of 30 pF.

- These I/Os must not be used as a current source (e.g. to drive an LED).

4. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after

reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC

www.st.com.

5. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1).

6. If the device is delivered in an UFBGA176 or WLCSP90 and the BYPASS_REG pin is set to VDD (Regulator off/internal reset

ON mode), then PA0 is used as an internal Reset (active low).

Table 7. STM32F40xxx pin and ball definitions(1) (continued)

Pin number

Pin name

(function after

reset)(2)

Alternate functions

Additional

functions

Table 8. FSMC pin definition

Pins(1)

FSMC

LQFP100(2)

WLCSP90

(2)

NOR/PSRAM/

SRAM

NOR/PSRAM Mux NAND 16 bit

PE2

A23

Yes

PE3

A19

Yes

PE4

A20

Yes

PE5

A21

Yes

PE6

A22

Yes

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