STM32F405 datasheet(36/204 Pages) STMICROELECTRONICS

36 / 204 page

Description

STM32F405xx, STM32F407xx

36/203

DS8626 Rev 9

2.2.26

Audio PLL (PLLI2S)

The devices feature an additional dedicated PLL for audio I2S application. It allows to

achieve error-free I2S sampling clock accuracy without compromising on the CPU

performance, while using USB peripherals.

The PLLI2S configuration can be modified to manage an I2S sample rate change without

disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces.

The audio PLL can be programmed with very low error to obtain sampling rates ranging

from 8 KHz to 192 KHz.

In addition to the audio PLL, a master clock input pin can be used to synchronize the I2S

flow with an external PLL (or Codec output).

2.2.27

Secure digital input/output interface (SDIO)

An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System

Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.

The interface allows data transfer at up to 48 MHz, and is compliant with the SD Memory

Card Specification Version 2.0.

The SDIO Card Specification Version 2.0 is also supported with two different databus

modes: 1-bit (default) and 4-bit.

The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack

of MMC4.1 or previous.

In addition to SD/SDIO/MMC, this interface is fully compliant with the CE-ATA digital

protocol Rev1.1.

2.2.28

Ethernet MAC interface with dedicated DMA and IEEE 1588 support

Peripheral available only on the STM32F407xx devices.

The STM32F407xx devices provide an IEEE-802.3-2002-compliant media access controller

(MAC) for ethernet LAN communications through an industry-standard medium-

independent interface (MII) or a reduced medium-independent interface (RMII). The

STM32F407xx requires an external physical interface device (PHY) to connect to the

physical LAN bus (twisted-pair, fiber, etc.). the PHY is connected to the STM32F407xx MII

port using 17 signals for MII or 9 signals for RMII, and can be clocked using the 25 MHz

(MII) from the STM32F407xx.

STM32F405 数据表(PDF) 36 Page - STMicroelectronics

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