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STM32F405 数据表(PDF) 22 Page - STMicroelectronics |
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STM32F405 数据表(HTML) 22 Page - STMicroelectronics |
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22 / 204 page  Description STM32F405xx, STM32F407xx 22/203 DS8626 Rev 9 Figure 6. Multi-AHB matrix 2.2.8 DMA controller (DMA) The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each. They are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth (AHB/APB). The two DMA controllers support circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. The two DMA controllers also have a double buffering feature, which automates the use and switching of two memory buffers without requiring any special code. Each stream is connected to dedicated hardware DMA requests, with support for software trigger on each stream. Configuration is made by software and transfer sizes between source and destination are independent. The DMA can be used with the main peripherals: • SPI and I2S • I2C • USART • General-purpose, basic and advanced-control timers TIMx • DAC • SDIO • Camera interface (DCMI) • ADC. ARM Cortex-M4 GP DMA1 GP DMA2 MAC Ethernet USB OTG HS Bus matrix-S ICODE DCODE Flash memory SRAM1 112 Kbyte SRAM2 16 Kbyte AHB1 peripherals AHB2 FSMC Static MemCtl ai18490d CCM data RAM 64-Kbyte APB1 APB2 peripherals |
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